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We are looking for exceptional software engineers to help develop the next generation chips based on a revolutionary architecture.
In this job you will design and develop software for functional and performance validation.

Key job responsibilities:
In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving channel behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.

We are seeking a passionate, Senior Analog Engineer to join our team. In this role, you will be responsible for designing and developing complex analog and mixed-signal ICs for SolarEdges cutting-edge products in the renewable energy sector. What will you be doing:
* Architecture planning using behavioral models for simulation of analog and mixed-signal circuits.
* Design, implement and verify circuits & systems to meet product requirements including schematic entry, simulation, layout and supervision.
* Verification of analog and mixed-signal sub-systems and the entire design using transistor-level.
* Validation of design by laboratory measurement.
* Support product engineering to meet manufacturing and production needs.

Country:
Israel
City:
Herzliya

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

We are hiring a Senior PCIe Firmware to the Chip Design PCIe Firmware team. You will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation our devices in a wide range of fields - low-level C layer between HW and FWs, automation challenges, and Python testing environment.

What youll be doing:

implement FW and verification features in a pre and post silicon environments in the PCIe technology.

Collaborate with other teams in the PCIe group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods.

Improve the existing automated process.

The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.
The team collaborates with the BackEnd team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin-out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on Package substrate layout, with a blend of Signal & Power integrity extractions and simulations, as well as also influencing the DIE I/O structures.

Key job responsibilities:
Design and Layout of large and complex package substrates.
Understanding package substrate technologies and layout design rules.
Proficiency in Signal and Power Integrity considerations.
Layout test studies of Die bump-out structures and Package substrate breakout.
Layout test studies of Package pin-out arrangements and PCB board implementation.
Continuously improve the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.

The position is for an entry level, and we will teach and mentor all aspects of the role. No prior hands-on experience in the above list is required.

We are seeking a sharp, innovative, and hands-on Architect to help shape the future of LLM inference at scale. Join our dynamic E2E Architecture group, where we build cutting-edge systems powering the next generation of generative AI workloads. In this role, you will work across software and hardware domains to design and optimize inference infrastructure for large language models running on some of the most advanced GPU clusters in the world.

Youll help define how AI models are deployed and scaled in production, driving decisions on everything from memory orchestration and compute scheduling to inter-node communication and system-level optimizations. This is an opportunity to work with top engineers, researchers, and partners across us and leave a mark on the way generative AI reaches real-world applications.

What Youll Be Doing:

Design and evolve scalable architectures for multi-node LLM inference across GPU clusters.

Develop infrastructure to optimize latency, throughput, and cost-efficiency of serving large models in production.

Collaborate with model, systems, compiler, and networking teams to ensure holistic, high-performance solutions.

Prototype novel approaches to KV cache handling, tensor/pipeline parallel execution, and dynamic batching.

Evaluate and integrate new software and hardware technologies relevant to Core Spectrum-X technologies, such as load balancing, telemetry, congestion control, vertical application integration.

Work closely with internal teams and external partners to translate high-level architecture into reliable, high-performance systems.

Author design documents, internal specs, and technical blog posts and contribute to open-source efforts when appropriate.

This position is intended for a candidate with a background in security engineering who is looking to transition into a cybersecurity architecture role. The role focuses on reviewing cloud and SaaS environments, assessing the effectiveness of security controls, and supporting security maturity assessments and mitigation planning activities.This is a junior‑level architecture role with an emphasis on technical analysis, control review, and security design assessment. The position prioritizes architectural evaluation and advisory activities over hands‑on implementation.

Responsibilities
Perform security maturity assessments, including reviews of technical controls, configurations, and architectural designs, aligned with the NIST CSF 2.0 cybersecurity framework.
Conduct technical configuration and control reviews of cloud environments and SaaS platforms (read‑only / observer role).
Analyze security architectures and technical implementations to identify gaps, risks, and improvement opportunities.
Translate technical findings into clear architectural observations and recommendations.
Produce structured assessment reports and technical findings for both technical and non‑technical audiences.
Maintain internal technical documentation and contribute to architectural knowledge within the team.
Collaborate with R&D and product teams on ad‑hoc cases as a cybersecurity technical subject‑matter contributor.

We are seeking a Software Engineering Architect to join the company Tableau engineering team. You will be instrumental in designing and architecting complex, data-driven software systems at scale, with a heavy focus on delivering a best-of-breed Semantic Layer for AI-based data analytics capabilities. As a key technical leader, you will shape the architecture, guide engineering teams in standard methodologies, and ensure the scalability, reliability, performance, and security of our products. You will work on high-impact projects and collaborate closely with Principal Architects.
Your Impact:
Architectural Design & Strategy: Define secure, scalable, and resilient architecture for large-scale, distributed, high-performance systems across multiple cloud environments. Ensure technical solutions align with customer needs, platform, other teas and business requirements.
Semantic Layer & AI Focus: Design, evolve, and govern the next generation of our semantic layer and data modeling framework. Drive the leverage of AI (LLMs and more) and analytic agentic capabilities by providing a unified, rich, and performant data interface.
Execution & Ownership: Be hands-on: write code and POCs, engage in pull requests, and remain close to the code. Simultaneously handle multiple complex, high-priority projects, ensuring architectural decisions support short- and long-term business objectives.
Technical Leadership & Optimization: Provide leadership and mentorship to engineering teams. Lead efforts to optimize system performance and scalability, and ensure high availability and resilience.
Collaboration & Documentation: Work closely with multi-functional teams (PMs, AI experts, engineers, and stakeholders) to define and implement architectural strategies. Create comprehensive documentation for architectural designs and decisions.

We are looking for a Salesforce Solution Architect to lead the design and evolution of Cynet’s Salesforce ecosystem. In this role, you will own the end-to-end architecture of Salesforce and its integrations across the company’s GTM and operational systems, enabling scalable processes that support rapid global growth. Responsibilities
* Own the end-to-end solution architecture for Salesforce and related business systems across GTM and operational teams
* Partner with business and technical stakeholders to shape scalable solutions that support rapid growth and long-term maintainability
* Lead discovery sessions, gather requirements, and translate business needs into clear solution designs across configuration, automation, custom development, integrations, and data architecture
* Design scalable Salesforce architecture across Sales Cloud, Service Cloud, Experience Cloud, CPQ, and adjacent business applications where relevant
* Define and govern core architecture decisions including data model, security model, role hierarchy, permission design, sharing model, environment strategy, and platform standards
* Design and oversee integrations between Salesforce and other business systems such as ERP, CPQ, marketing automation, support platforms, and internal tools
* Evaluate tradeoffs between declarative and programmatic solutions, and recommend the right approach based on scale, complexity, maintainability, and business impact
* Provide technical leadership for implementation, including flows, Apex, LWCs, APIs, async processing, and deployment strategy
* Establish governance and best practices for release management, testing, documentation, technical debt reduction, and solution scalability
* Collaborate closely with Sales, CS, Finance, Marketing, RevOps, and MIS to ensure alignment, adoption, and high-quality delivery
* Support hands-on solution delivery when needed, including configuration, troubleshooting, code review, and production issue resolution
* Build architecture documentation including solution diagrams, design decisions, process flows, and system landscape mapping
* Monitor platform health, usage, and business application ecosystem maturity to support scale, compliance, and operational efficiency

About Us:
Cynet is a leader in threat detection and response, designed to simplify security for organizations of all sizes. Our mission is to empower lean security teams and their partners with an AI-powered, unified platform that autonomously detects, protects, and responds to threats - backed by 24×7 security experts. With a Partner First mindset , we focus on helping customers and partners stay protected, operate confidently, and achieve their goals. Our vision is to give every organization true cybersecurity peace of mind, providing fast, accurate protection without the noise or complexity.

Required Fraud Lead (Technical Architect)
Tel Aviv-Yafo, Gush Dan, Israel
We offer the industrys only platform that fuses customer identity and anti-fraud solutions - customer identity management, identity verification, and fraud prevention.
We sell to industries with large, consumer-facing businesses such as: banking, financial services, insurance, fintech, gaming, ecommerce/retail, telco / media, utilities, etc.
About the Role:
The Fraud Lead is the principal technical authority for our fraud detection and response engine. You own the professional logic that powers our product, ensuring that the "Brain" of our platform is technically cohesive, scientifically rigorous, and market-leading.
You act as a System Architect for the fraud domain, connecting the dots between Research, Data Science, and Analytics. Crucially, you serve as the primary technical consultant for our customers, helping them understand, integrate, and optimize the fraud logic that protects their environments. You work alongside a separate Product group (who defines the roadmap) and a Platform Engineering group (who builds the infrastructure).
What youll do:
Technical Domain Architecture
Logic Blueprinting: Design the end-to-end technical logic for detection features-from telemetry ingestion to real-time response actions.
Cross-Team "Glue": Ensure that Fraud Research insights are effectively operationalized by the Data Science team and surfaced correctly by the Analytics team.
Architecture Governance: Set the technical standards for how detection logic is built, ensuring it is scalable and compatible with the Platform Engineering teams infrastructure.
Customer Fronting & Technical Advisory
Technical Subject Matter Expert: Act as the lead technical consultant for high-value customers. You will lead "deep-dive" sessions with client-side engineers and fraud experts to explain our detection methodologies and data requirements.
Integration Strategy: Advise customers on how to best leverage our technical logic within their specific business contexts.
Feedback Loop: Translate complex customer technical needs and "edge case" fraud patterns back into technical requirements for the internal fraud group.
Expert Implementation
Hands-on Prototyping: Remain an expert practitioner in Python and SQL. You will prototype new detection methodologies and perform technical validation of production models.
Quality & Observability: Design the technical frameworks that ensure our detection logic remains performant and observable in live customer environments.