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Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.

Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

Technical Lead, Custom Digital Circuit Design, Mixed Signal
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As the Lead Architect for our custom back-end solutions for high-speed internal connections, you will set the design standards for our custom silicon. You will ensure our physical design methods can support data speeds of 1.6T and above while maintaining high manufacturing reliability and performance. You will create the design framework for our future hardware, solving complex engineering challenges in the latest manufacturing processes.
Responsibilities
Define the global back-end and custom Physical Design methodology, driving the transition to automated Analog and Mixed-Signal (AMS) flows and "Layout-Aware" design.
Lead full custom digital circuit design at the transistor level optimized for low power.
Evaluate and de-risk new process features in GAA (Gate-All-Around) nodes (e.g., Backside Power Delivery, Buried Power Rails) for high-speed analog use cases.
Drive the long-term Roadmap for Area and Power density, ensuring our PHYs remain the most efficient in the industry.
Act as the primary liaison with foundries to optimize Design for Manufacturing (DFM) and maximize yield for massive TPU-scale chips.

Required IP Design Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System-on-a-Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high-quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Establish IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

We are looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.
Take part in the development of state-of-the-art products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the world's largest cloud provider, in a dynamic, open, and fast-paced environment.

We are looking for talented engineers to join our Chip Design team, working on the Graviton product line. Our chip design team is in charge of defining the product's features and working on their architecture and development. Our team members collaborate with multiple teams from different disciplines such as product definition, pre and post silicon validation, physical design, software and others contributing to a full cycle of chip development from idea to mass production. Your design will be integrated into the Graviton products, an important part of the AWS data centers worldwide. This is an opportunity to have a large-scale impact.

Key job responsibilities
Own a domain or sub-domain within an SoC - Take full responsibility for its entire lifecycle: Architecture and micro-architecture definition Writing RTL code in Verilog. Supporting the Verification and Emulation teams with test planning, debug, and results review Ensuring the final chip meets quality and reliability standards Collaborating with cross-functional teams - Partner with Product Definition, Verification, Emulation, Software, and Silicon Integration teams to deliver cohesive solutions.

We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join accelerators IP group in Beer-Sheva, working on RiscV processor IPs.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development: Verification, Design.

Work closely with Firmware and other groups around the globe.

Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team

AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.

You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.

Responsibilities

Lead the software architecture and technical roadmap for or next-generation ultra low-latency AI-SuperNIC software stack, including drivers, firmware, libfabric, and libibverbs.
Define the partitioning and interfaces between hardware, firmware, kernel drivers, user-space libraries, and AI frameworks.
Lead the design and implementation of high-performance networking, RDMA, and GPU-direct communication capabilities.
Drive software support for emerging technologies and standards such as UEC, UALink, MRC and RoCEv2 ecosystems.
Work closely with hardware, system architecture, and VLSI teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership across firmware, driver, and networking software development

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Required Senior System Architect for ECU designs
About the team:
We are at the forefront of developing autonomous driving systems with leading OEMs, by integrating our state-of-the-art ECUs into various vehicles.We are developing advanced automotive ECUs for next-generation vehicle functions. Our programs require a robust end-to-end verification strategy that ensures design correctness, safety, and performance across complex HW/SW systems and multiple suppliers
In this role, you will own the system architecture for our ECU designs-from defining the verification concept and traceability, through specifying verification environments and evidence, to leading technical alignment across hardware, embedded software, and validation teams.Youll collaborate with architects, design engineers, verification leads, and suppliers to deliver high-quality ECU platforms to OEMs and Tier 1s. Your work will directly influence product quality, time-to-market, and readiness for customer reviews and audits.
What will your job look like:
Engage directly with customers to analyze requirements and negotiate existing solutions to meet their needs.
Define system requirements and architecture that align with customer needs and integrate with our software (SW) and hardware (HW) products.
Collaborate with Product Management to ensure architectural coherence across the entire product lines.
Work closely with Project Managers to define and prioritize engineering R&D scopes and product release dependencies.
Drive cross-functional technical alignment: Work with HW, embedded SW, system architects, and validation leads to ensure designs are verifiable (DFV), interfaces are testable, and assumptions are reviewed and documented.
Ensure compliance with ASPICE Level 2 standards for System and Software Requirements and Architecture.
Own risk management and escalation: Identify verification gaps and high-risk features; propose mitigation plans and drive execution across teams.

We are looking for a passionate and experienced System Architect to lead the definition and evolution of validation methodologies for complex multidisciplinary systems. In this role, you will combine deep system-level understanding with extensive validation expertise to drive platform validation strategies, identify technical risks, influence architectural decisions, and ensure the quality, robustness, and reliability of our products throughout the development lifecycle.
What will your job look like?
Develop a deep understanding of the system architecture and its implementation across all platform features and domains.
Define, own, and drive feature-level and platform-level validation strategies, leveraging positive, negative, boundary, fault-injection, robustness, integration, and architectural validation methodologies to ensure comprehensive system verification and risk mitigation.
Derive and define platform-level validation requirements, methodologies, coverage models, validation criteria, and acceptance criteria that complement and extend existing system requirements.
Identify validation gaps, testability challenges, architectural weaknesses, and technical risks early in the development lifecycle.
Review platform architecture and design decisions, providing validation-driven feedback to improve quality, reliability, robustness, and testability.
Influence architectural decisions through validation findings, root-cause investigations, technical analysis, and data-driven recommendations.
Lead root-cause analysis of complex system-level issues and drive resolution across multidisciplinary engineering teams.
Serve as the technical focal point for validation-related architectural discussions, methodologies, and best practices.
Collaborate closely with system architects, developers, and validation engineers to ensure validation considerations are integrated throughout the product development lifecycle.
Drive continuous improvement of validation methodologies, tools, processes, and coverage across the platform.

We are looking for a Storage Software Architect to join the architecture group. You will be part of a team that shapes the next generation of storage for AI: training, inferencing, KV cache, RAG and more. Utilizing the best from our network products, DPUs and NICs, working closely with hardware architects, SW architects and external customers, defines the programming interfaces, protocols and management. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow. We work, think and learn as a team. We thrive in a deeply strong environment and we're passionate about a culture that demands innovation and the highest standards. The rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.

What youll be doing:

Define how storage for AI clusters should look like.

Research and analyze AI storage workloads, POC ways to optimize them.

Design the storage SW stack for AI, APIs, and offloads.

Lead hands-on POCs.

Drive HW features to next generation of DPUs and NICs.

Required Director of Technology and Architecture
So, whats the role all about?
The Director of Technology and Architecture owns the technical vision that holds this portfolio together. The mandate is to ensure that a wide-ranging set of products remains coherent, secure, scalable, and economical to build and operate regardless of where and how it is deployed. This is a hands-on leadership role at the intersection of deep technical authority and enterprise strategy: you will set architectural direction, resolve the hardest cross-cutting trade-offs, and raise the engineering bar across the organization.
This is the most senior individual-contributor-plus-leadership technical role in the company. You will be a trusted advisor to the executive team and the final technical authority on architecture decisions that span products.
How will you make an impact?
Architectural Vision & Strategy:
Define and own the multi-year target architecture across the entire product suite, balancing product autonomy with shared platform leverage.
Establish an architecture strategy so that products can be delivered on-premise, in private cloud, in public cloud, or as pure cloud SaaS.
Drive the platform and shared-services strategy (identity, data, integration, observability, deployment tooling) that reduces fragmentation across products.
Help architects translate business and product strategy into technical roadmaps; advise the executive team on build-vs-buy, modernization, and major technology bets.
Design abstractions and packaging models that let a single product run reliably across heterogeneous environments with differing scale, network, data residency, and operational constraints.
Establish reference architectures and patterns for tenancy, configuration management, release/upgrade cadence, and feature parity across on-premise and cloud-hosted deployments.
Security, Compliance & Resilience:
Embed security, privacy, and regulatory compliance into the architecture by design - addressing the standards relevant to financial services (e.g., data protection, auditability, segregation, encryption, and regional data residency).
Define non-functional requirements and architectural guardrails for availability, disaster recovery, transactional integrity, performance, and observability appropriate to mission-critical financial systems.
Partner with Security, Risk, and Compliance leadership to ensure the architecture withstands audit and regulatory scrutiny across jurisdictions.
Governance & Standards:
Establish and run an architecture governance function: standards, decision records, review processes, and a technology radar - proportionate enough to enable speed rather than obstruct it.
Evaluate and select core technologies, platforms, and strategic vendors; own the long-term technology stack direction.

We are seeking a Senior Principal Software Architect to define and drive the long-term architectural vision for our Identity Platform. In this role, you will lead the design and evolution of our next-generation Identity services, ensuring they meet the highest standards of scalability, security, resiliency, and operational excellence. As one of the organization's senior technical leaders, you will shape architecture across multiple product areas, influence strategic technology decisions, and partner with Engineering, Product Management, Security, and Architecture leadership to build a world-class Identity platform. You will establish architectural standards, mentor engineering teams and architects, and drive modernization initiatives that accelerate innovation while reducing technical debt.
Key Responsibilities
Define and evolve the long-term architecture and technology strategy for the Identity Platform.
Lead the design of large-scale, cloud-native SaaS systems that meet demanding scalability, security, availability, and performance requirements.
Establish architectural principles, design standards, and engineering best practices across multiple teams and organizations.
Partner with Product Management, Engineering, Security, and fellow architects to translate business and cybersecurity requirements into scalable technical solutions.
Drive modernization initiatives, simplify complex systems, and strategically reduce technical debt.
Lead architecture reviews, identify technical risks, and guide teams toward successful implementation.
Mentor architects and senior engineers, fostering technical excellence and growing future technical leaders.
Represent the Identity organization in architecture forums and contribute to the broader engineering strategy across Palo Alto Networks.

we are looking for a Principal Architect.
You own the end-to-end architecture of the agentic platform: how speech, avatar generation, and the agentic reasoning layer combine into one coherent system that holds up in production, across many tenants, under a real-time latency budget.
This is the widest technical seat in the group. A single user turn crosses speech recognition, retrieval, planning and tool calling, speech synthesis, and avatar rendering, and the experience is only as good as the seams between them. The scope here is the whole path, including the parts we did not build ourselves: externally sourced capabilities, third-party model providers, and customer-owned systems reached through the gateway.
Some of the decisions here shape the platform for a long time: how the speech pipeline is composed, which real-time orchestration and transport framework the platform standardizes on, how new capabilities are absorbed into the target architecture, and where a shared component belongs versus a per-customer one. You define the criteria these decisions are judged against and work closely with the research team that benchmarks the options, so the call rests on evidence. You write the reasoning down, and you stay close enough to the code to know when reality disagrees with the design.
You are hands-on. You prototype to de-risk, you read the traces yourself, and you stay as close to the numbers as to the diagram.