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As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

The production TEST team - responsible for the definition, development, and deployment of production TEST operations for the worlds most advanced socs for adas and self-driving vehicles.
this is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
what will your job look like?
work closely with design and TEST engineers from the earliest development phases to review chip electrical and mechanical specifications and define the hardware architecture and requirements for load boards (lb) and probe cards (pc).
lead and oversee all aspects of lb and pc development, including schematics, bom selection, pcb layout, pi/si simulations, and mechanical design.
define, guide, and validate testsocket requirements, specifications, design, and electrical performance.
establish electrical and mechanical specifications for custom RF modules integrated into the complete TEST system architecture.
manage supplier interactions and logistics, ensuring accurate tracking of manufacturing status, delivery schedules, Quality Assurance, and repair/rma processes.
own hardwarereadiness activities, including validation, qualification, and release of TEST hardware into engineering and production environments.
support postsilicon testprogram debug efforts, resolving hardwarerelated issues and enabling timely delivery of samples to internal and external customers.

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team at our company works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing. 
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements! 
 
what youll be doing: 
you will be in charge of state of the art design for TEST /atpg flows and implementation 
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis. 
inventing and maintaining automation flows that provide the short TEST time to production

we are looking for a senior Verification engineer to join our fullchip switch silicon team. as a fullchip Verification engineer at our networking business unit, you'll join a group of passionate and talented engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a full chip verification team that is responsible to integrate and verify our switch products at system level
work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the switch
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

We are currently seeking a Senior FPGA Engineer to join one of our trading teams. While our company has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. Were seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
Responsibilities:
Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
Research and evaluate a variety of cutting-edge FPGA hardware and technologies
Propose creative solutions to overcome FPGA/hardware limitations
Liaise directly with software and other design teams
Conduct lab debugging and characterization of new hardware.

In this role, you will be a key contributor to the design and implementation of AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.

You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of NPU embedded solutions, actively promoting AI capabilities to the customers.

What will you do:

Own and design key components of the AI Graph Compiler software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.

Join CIO Architect team and shape the future of AI! We're seeking a hands-on AI Solutions Lead to lead the development and implementation of enterprise-wide AI applications. In this pivotal role, you'll evaluate and deliver cutting-edge AI solutions to employees and teams across the organization. You'll spearhead AI solution projects from initial concept and requirements gathering through execution and widespread adoption, serving as the central point of contact between business, IT, and Data teams. You'll also stay at the forefront of the latest AI technologies.
As an AI Solutions specialist (CIO Group) you will
Collaborate with cross-functional teams to diagnose challenges and opportunities where GenAI and AI Agent can provide real, measurable value.
Lead the lifecycle of GenAI-driven applications and Autonomous Agents, transitioning rapidly from initial concept and technical feasibility to full enterprise-grade production roll-outs.
Conduct technical audits of emerging AI technologies, leading "Build vs. Buy" analyses to ensure global scalability, security, and measurable value to the organization.
Run training and enablement sessions for both technical and non-technical teams, fostering a culture of AI literacy and ensuring the organization can leverage new tools effectively.
Build and evolve the Enterprise AI technology stack, continuously scouting and integrating next-generation platforms, LLM orchestration tools, and agentic frameworks.
Serve as the primary technical liaison between IS, IT, Legal, and Data teams to ensure AI solutions are securely integrated and compliant with enterprise standards.
Own the long-term roadmap and administration of enterprise AI platforms, driving continuous solution adoption, impact measurement, and performance optimization across the organization.

We are looking for a highly technical, customer-obsessed Senior Technical Leader to define and drive the usability, integration standards, and provisioning for these cutting-edge technologies. In this role, act as the technical champion for the DPU, ensuring our software stack and tools are robust, performant, and intuitive from day one. By bridging the gap between core R&D and real-world deployments, this position directly shapes how seamlessly the world's largest data centers adopt our platform.


What youll be doing:

Own the end-to-end BlueField and DOCA lifecycle, from out-of-the-box installation and configuration through field updates, provisioning, functionality, documentation, and performance.

Act as the essential bridge between R&D and the real world by collecting operational feedback from customers and internal stakeholders (developers, architects, integration teams, and QA).

Translate complex deployment friction points and customer pain points into actionable engineering requirements and architectural direction.

Perform hands-on prototyping, scripting, and system-level validation-installing the product, reproducing scenarios, and analyzing logs-to continuously elevate the platform.

Collaborate deeply with Core R&D, QA, and Solutions Architecture to guarantee new features meet strict usability standards.

In this role, you will be the architect of our "security brain." You will write the low-level code that observes what is happening (eBPF/Golang) and build the AI models that understand, diagnose, and prevent issues (LLMs/Python).
Key Responsibilities
1. The "Eyes": eBPF Development & Systems Engineering
Lead the Cimon Agent: Spearhead the active development of our high-performance eBPF agent "Cimon" using Golang and C.
Kernel-Level Innovation: Design and implement eBPF programs for deep observability, runtime security, and container monitoring.
Performance Obsession: Write beautiful, highly efficient code that runs in the Linux kernel with minimal overhead.
Community Leadership: Actively participate in the eBPF and open-source communities, contributing code and presenting technical deep dives at conferences.
2. The "Brain": AI Innovation & Security Research
AI-Driven Security Solutions: Architect and prototype models for:
Automated Exploitability: Checking SAST/SCA findings for validity.
AI Remediation: Automatically fixing Dockerfile misconfigurations and generating patches.
Model Detection: Identifying AI models embedded within codebases.
Benchmarking & Rigor: Design evaluation frameworks to measure model accuracy, false positives, and robustness in security contexts.
Prompt Engineering: Shape prompt strategies and workflows to translate real-world security challenges into actionable AI logic.
3. The Intersection: Collaboration & Evangelism
Cross-Functional Leadership: Serve as the technical link between the AI development team and the core security engineering team.
Thought Leadership: Author whitepapers, technical blogs, and deliver talks on the cutting edge of "AI for Systems Security."
Mentorship: Guide engineers on best practices for both low-level systems design and AI integration.
Why This Role?
No Context Switching Cost: You won't just be researching; you will be building the tools you research. You control the data collection (eBPF) and the analysis (AI).
Deep Tech Focus: This isn't a wrapper-API role. You will be dealing with kernel bypasses, memory safety, and LLM hallucinations all in the same week.
Impact: Your work will directly power the next generation of automated security remediation.

Based in Israel, youll serve as the technical expert and strategic advisor throughout the sales process - from discovery to demo to deployment. Whether its architecting a high-scale solution, answering in-depth questions, or running a proof of concept, your expertise will be key to helping customers realize the power of Aerospike.

This is a pre-sales position.

Responsibilities:

Preparing and developing technical presentations to explain our company's products or services to customers.

Discussing equipment needs and system requirements with customers and engineers.
Collaborating with sales teams to understand customer requirements and provide sales support.
Researching, developing, and identifying modifying products to meet customers' technical requirements and needs.
Soliciting and logging client feedback and evaluating the data to create new sales and marketing strategies to target customers.
Identifying areas for improvement and communicating these issues as well as possible solutions to upper management, including product managers.
Setting and achieving sales goals and quotas.
Training other members of the sales team on the technical aspects of the company's products and services.

Data has never been more valuable and vulnerable. As cybercriminals become more sophisticated and regulations more strict, organizations struggle to answer one key question: Is my data safe?"
At our company, we see the world of cybersecurity differently. Instead of chasing threats, we believe the most practical approach is protecting data from the inside out. Weve built the industrys first fully autonomous Data Security Platform to help our customers dramatically reduce risk with minimal human effort. At our company, we move fast. Were an ultra-collaborative company with brilliant people who care deeply about the details.
Together, were solving interesting and complex puzzles to keep the worlds data safe.
We work in a flexible, hybrid model, so you can choose the home-office balance that works best for you.
The FinOps Technical Manager leads cloud cost operations, driving cost optimization and governance across multi-cloud environments. This role combines technical expertise with strategic leadership to align cloud spend with business objectives while fostering a culture of cost accountability.
Key Responsibilities:
Strategic Leadership
Champion cost-awareness across teams and influence architectural decisions for efficiency.
Lead cross-functional initiatives to improve cloud economics and operational excellence.
Team Management
Provide hands‑on technical guidance on cloud architecture, cost‑efficient design patterns, and optimization best practices. Foster strong collaboration between finance, DevOps, and engineering teams to ensure shared ownership of cloud costs
Cloud Cost Management
Monitor and analyze cloud spend across AWS, Azure, and Kubernetes clusters.
Identify optimization opportunities by diving into current system architecture/ flows and implementation and resent actionable recommendations to leadership.
Be able to challenge current and future technological and architecture decisions in favor on cost optimization.
Ability to detect bad designs and implementations that cause high spend.
Automation & Tooling
Oversee automation of cost reporting and anomaly detection.
Evaluate and implement tools and integrations for real-time visibility.

as a senior QA professional, you will be collaborating with a saas development team, that use the latest technologies in continuous delivery to secure the top enterprises in the world.
gain a deep understanding of the product's functionality, target use cases, and the value it provides to customers.
serves as the senior QA professional in the r&d team
commit to the quality of all released content
take an active role in process inspection and continuous improvement
actively track team tasks, analyze testing needs, and define QA activities and ownership
plan, define, and execute tests as part of team QA related activities
analyze and challenge existing testing coverage, both manual and automated
create TEST plans to determine the steps needed to increase confidence in product quality
monitor the TEST and production environments, using DevOps tools assimilate appropriate QA activities within every step of the sdlc
define, implement, and manage QA processes, including TEST plans and procedures
actively participate in feature testing during development to ensure adherence to specifications and quality standards
efficiently analyze logs and reproduce customer issues for quick resolution
maintain and prioritize open issues and bugs to ensure effective tracking and resolution
monitor TEST and production environments using DevOps tools and methodologies.
design and execute automated tests, manage TEST environments, and develop tools to improve testing efficiency and coverage. qualifications
at least 5 years of experience in QA roles, deep understanding of QA methodologies
proven experience in system analysis and excellent business requirements understanding
experience in TEST design and execution for complex systems (manual and automated)
proficiency in analyzing rest api interactions originating from UI workflows
broad understanding of complex product solutions (business, technical, architecture)
demonstrated ability to design and write new tests for system -level scenarios
proven experience with saas product sdlc, preferably on aws
comprehensive experience working in an agile development process
proactive mindset and a passion for excellence and continuous improvement
curiosity and self-learning skills; ability to collaborate cross-functionally
soft skills:excellent time management and ability to deliver high-quality results on schedule
proactive by nature; internal drive for excellence and improvement
team player
ability to work alone
capability to manage task priority effectively fluent english security testing background
experience in performance, and scale tests
experience in datadog and production monitoring
experience with aws
experience with sdlc of saas products
experience with Linux and ssh
hands-on experience with automated testing tools
experience in writing of automation tests
knowledge in Python

We are looking for a strong, motivated and super technical FrontEnd R&D Tech Lead to join the Web & Cloud management group.
Job Id: 24615
This Leader will co-own the Web SmartConsole platform, design & develop Infrastructure components along with the I/S team, work with application teams to mentor and review. Web SmartConsole is the Client that enables customers to use our services over the web and support the growth of our activity on the cloud.
Key Responsibilities:
Work very closely with the Web SmartConsole I/S team and Co- lead the design & development of I/S components (along with the Team Leader), This is to expand the unique FE I/S library and design system (which are all owned by the I/S team and this Tech Lead).
Work with the adjacent features teams (developing features over Web SmartConsole) be a mentor and gate keeper for quality FE development on Web SmartConsole.
Co-lead (with the Team Leader) the Web SmartConsole architecture, evolution of the technology stack and developer experience.
Contribute to improving the extensive CI/CD of Web SmartConsole (I/S and Features) that is agile and reaches customers (Cloud and on Prem) every sprint. Push for further improvements, cycle shortening and elegance for a demanding pipeline
Foster a culture of innovation, technical leadership, collaboration and teamwork with all teams.