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HW Application Engineer - Job description: we are a leading supplier of microcontrollers and security hardware solutions for tier-1 customers in the computing and servers business. It is a self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production. The group works closely with major customers, primarily key OEMs in the computing space, to develop semi-custom, innovative solutions for a wide range of application platforms. We are looking for a Hardware Application Engineer, to maintain and support our strong collaboration with our customers.
What You Will Be Doing
* Lead customers through all stages of designing their systems based on Nuvoton manageability and security microcontrollers (i.e., BMC, EC, SIO and TPM) from planning till production.
* Respond and resolve customer hardware related issues and requests, reported by the regional support team (FAEs) or directly by customers.
* Work closely with R&D, architects and PMs to provide issue resolutions, workarounds, and implement product features or support tools.
* Key contributor in complex debug tasks for issues found by customers; build debug strategies and hands-on work with the design team through the debug.
* Develop deep knowledge of customer applications and systems, recommend application solutions, design ideas and products to customer design teams.
* Develop and maintain technical documentation (e.g., reference schematics, application notes, design guidelines).
* Provide inputs and participate in next generation ICs definition based on customer inputs.
* Contribute to the definition of innovative and differentiated products.

Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

Required SoC Test Engineer Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, defective parts per million reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and return merchandise authorization handling.
Drive product leadership for silicon engineering organization from architectural definition to global availability.
Collaborate with cross-functional teams across the globe including ATE and SLT test engineering, quality and reliability, packaging, supplier management and operations to build, deploy, and maintain a high volume manufacturing screening solution.
Manage database integration and advanced usage for wafersort, final test, SLT and burn-in, test program integration, optimization, release to production, binning handling upon need, manufacturing flow definition and implementation, material handling during NPI, skew definition, process optimization with foundry.

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.

Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.

Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.

Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.

Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.

Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.

Develop SoC test and calibration capabilities for chip, module, and product factories.

Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes

Imagine what you could do here. At our company, new ideas have a way of becoming extraordinary products very quickly.
Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at our company .Do you want to join us to help deliver the next groundbreaking our products?

The company SoC design team is looking for an experienced engineer to develop our compute SoCs power management system. Role expectations include working with partner Design teams, Physical design, verification, Platform Architecture and Software teams to define the power system micro architecture, implement the required HW and integrate it to a complex multi chip system.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are seeking a highly skilled Emulation Engineer with extensive experience in the semiconductor industry to join our Chip Design team.

The ideal candidate will have a proven track record working with advanced emulation platforms, particularly Veloce, Palladium or Zebu.

Key Responsibilities:
Develop and maintain emulation models from RTL for complex SoC designs
Port RTL designs into emulation platform.
Debug hardware and software issues in pre-silicon environments.
Collaborate with frontend design, design verification, validation and software development teams to create comprehensive test strategies.
Set up and maintain emulation hardware infrastructure.
Develop workflows for efficient emulation processes.
Collaborate with emulator vendor field service engineers to resolve hardware issues.
Support users and debug issues.

Required Senior CAD Infra Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs.
Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow.
Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.

As a Salesforce Solution Architect, you will design and implement Salesforce solutions for our clients. You will collaborate with various stakeholders to understand business requirements and translate them into scalable and efficient Salesforce solutions. The ideal candidate will have a solid technical background in Salesforce, with demonstrated expertise in architecture design and implementation. We want to hear from you if you are passionate about Salesforce and enjoy working in a dynamic and challenging environment.

Responsibilities:

Designed and implemented Salesforce solutions for clients, ensuring scalability, efficiency, and best practices
Collaborate with stakeholders to understand business requirements and translate them into technical solutions
Lead and participate in project planning and estimation activities
Provide guidance and mentorship to development teams on Salesforce best practices and design patterns
Collaborate with cross-functional teams to integrate Salesforce solutions with other systems
Identify and resolve technical issues and challenges, driving continuous improvement and optimizing Salesforce solutions
Stay up-to-date with Salesforce platform updates, new features, and industry trends to provide innovative and effective solutions

We are looking for an experienced Threat Researcher to join our Solution Architect team. This role combines deep cybersecurity research with hands-on work in customer and PoC environments, helping uncover real-world attack scenarios, demonstrate security value, and translate field insights into product capabilities.
Responsibilities
Analyze network devices, configurations, security products, and customer environments to identify security risks and attack opportunities.
Research and develop methods to discover network topology, device relationships, attack paths, and lateral movement opportunities.
Conduct security assessments to identify weaknesses and recommend effective detection and mitigation strategies.
Research and analyze emerging cyber threats, attack techniques, and adversary behaviors.
Drive hands-on threat research in customer and PoC environments, simulating and validating real-world attack scenarios through our Securitys platform.
Develop tools, scripts, and frameworks to automate security and network analysis.
Translate research findings into actionable customer insights, detections, and product capabilities.
Collaborate with Solution Architects, R&D and Product teams to integrate new research capabilities into the platform and deliver value to customers.
Act as a cybersecurity subject matter expert for our customers.
Generate and present a comprehensive and professional report of findings from investigations.

Architectural leadership of the enterprise DWH project in an AWS cloud environment. The role focuses on designing robust data infrastructure, establishing the technological roadmap, and enabling seamless large-scale data processing to support BI and AI initiatives.

Key Responsibilities:

Lead the architectural design and implementation of the new enterprise DWH project.
Design, develop, and optimize complex cloud-based data solutions for processing massive datasets.
Select and implement the optimal AWS services (Redshift, Glue, Athena, EMR) and data formats (Parquet, Iceberg) for the core data stack.
Provide technical leadership, mentorship, and professional guidance to the Data Engineering team.
Collaborate closely with development teams, Data Scientists, and end-users to define requirements and deliver innovative Data and AI solutions.

Required Principal/ Senior Principal Software Engineer | Cortex Detection team
Job Summary:
Cortex is expanding. We combine the high energy of a startup with the massive resources of the worlds cybersecurity leader. We aren't just processing data; we are managing hundreds of petabytes of it, waiting Cortex for you to apply your "magic" to invent the next generation of threat detection. As a Principal Software Development Engineer, you will be a cornerstone of the Cortex Detection Backend team. This role is designed for a technical powerhouse who thrives in the "sweet spot" between high-level architectural strategy and hands-on execution. You will influence our product roadmap, mentor elite engineers, and build systems that protect thousands of the world's most sensitive organizations.
Key Responsibilities
Architect & Innovate: Design and build a new set of capabilities focused on Data Analytics and Threat Detection. You will solve cloud security challenges that have never been tackled before.
Scale Without Limits: Ensure our microservices architecture remains robust and resilient under massive loads, processing millions of events per second.
Technical Leadership: Act as a technical sounding board and mentor. You will guide design discussions, conduct deep-dive research, and foster a culture of engineering excellence.
Strategic Collaboration: Work closely with Product Management, R&D leaders, and Security Researchers to define requirements and turn ambiguous problems into elegant technical solutions.
Drive Execution: Take ownership of the software development life cycle, ensuring high-velocity delivery in a fast-paced Agile environment.

Were growing and looking to hire a Director of Data & AI who embodies our core values: People First, Customer Obsession, Strive for Excellence, and Integrity.
About the Company:
A global leader in cyber-physical systems (CPS) protection, dedicated to securing the critical infrastructure that keeps the world running. Were a fast-growing, award-winning team where innovation meets purpose-and we want you to help us define the future of cybersecurity.
Our technology strategy is focused on solving real-world cyber-physical security problems at scale through robust, distributed, cloud-native architectures. We design and evolve a unified platform that serves as the technological backbone for all our products, delivering deep visibility across CPS environments-without disrupting critical operations. Our architecture emphasizes scalability, resilience, and extensibility to support both cloud and on-prem deployments.
About the Role:
We are seeking a visionary Director of Visibility to lead our core technology engine. This is a highly unique role that demands both top-tier professional expertise in cybersecurity research and the ability to seamlessly integrate Data Science and AI in a precise, highly productive manner. We have ambitious visibility goals that require uncompromising accuracy. Your mission is to combine precise, in-depth professional understanding of Cyber-Physical Systems (CPS/XIoT) with the immense scale and capabilities of AI. You will lead a multidisciplinary group comprising Data Science, Network/Protocol Research, and Asset Classification teams to revolutionize how we discover, classify, and secure critical assets across industrial (OT) and healthcare (IoMT) environments.
Responsibilities
As a Director of Data & AI your impact will be:
Multidisciplinary Leadership: Manage, mentor, and synchronize three distinct teams (Data Science, Network Research, and Asset Classification), ensuring cross-functional synergy and unified product delivery.
Scaling Accuracy with AI: Architect our visibility solutions to achieve unparalleled precision. Blend deep professional domain knowledge with advanced ML to scale asset discovery without sacrificing the exactness required in critical infrastructure.
Feature Engineering & Parsing: Oversee the translation of obscure, undocumented industrial and medical protocols into actionable features for our AI models.
Cross-Department Collaboration: Work closely with various data groups, product management, and R&D teams to translate network visibility into actionable risk management, segmentation, and threat detection policies.
Advanced Data Fusion & Collection Strategy: Manage diverse collection techniques (passive, active, and integrations), and architect how to fuse information for every single device at the scale of AI-bridging applications, algorithms, LLMs, and beyond.

Required Sr MSIAM SOC Engineer (Unit 42)
Job Summary
As a Senior SOC Engineer within Unit 42, you will drive the creation, validation, and optimization of custom detection rules and automated playbooks across our global customer base. Acting as a trusted advisor, you will collaborate closely with clients to maximize their security posture using Cortex XSIAM and Unit 42 expertise. This highly analytical role leverages your deep understanding of detection lifecycles, proactive automation, and threat intelligence to secure enterprise environments. You will architect end-to-end security lifecycles that seamlessly connect data ingestion with high-fidelity detection engineering.
Key Responsibilities:
Own the full lifecycle of custom detections and response automations, deploying them as high-fidelity Cortex XSIAM correlation rules and playbooks through a rigorous engineering process of development, testing, staging, and soft implementation.
Drive the continuous refinement of correlation rules to ensure strict standards for performance, accuracy, and operational relevance.
Translate Unit 42 threat intelligence research and emerging adversary TTPs into actionable, robust detection logic.
Champion proactive automation by engineering sophisticated playbooks to resolve emerging security challenges and optimize operational workflows ahead of demand.
Architect the end-to-end security lifecycle within Cortex XSIAM, seamlessly connecting data ingestion, high-fidelity detection engineering, and sophisticated response automation.