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We are looking for a DSP expert for high-speed communication links. We are looking for an experienced and creative DSP expert to take part in the development in the design of very high-speed communication wireline links. This crucial role will give you a rare opportunity to make an impact on the industry through interactions with other industry experts, with the goal to enable the creation of future high-speed links that interconnect among computers and other devices. You should have a proven and deep understanding of DSP and communication theory. You will need to demonstrate strong industry experience in delivering high-quality production system software. You will take part in the development efforts for creating DSP architecture of future chips and enhance the functionality of currently shipping products. The ability to work in a dynamic and diverse team is required. Strong interpersonal skills and a real passion for working as a team are critical. If this sounds like a fun challenge, we want to hear from you!

What you will be doing:

You will take a technical position in a DSP team.

Collaborate with peers, peer engineering teams, and program/product management to ensure that product requirements, goals and objectives are met or exceeded.

You will work on architectural and technical solutions for high speed SERDESes.

looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

As the Silicon Engineering Manager you will be responsible for improving silicon-photonics yield and performance through data-driven analysis, cross-functional collaboration and proactive issue resolution.

You will serve as the key interface between R&D, Process and Production teams, ensuring efficient data flow, rapid issue identification and continuous process improvement across wafer fabrication, device testing, and packaging stages.

Responsibilities:
Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
Manage engineering approval forum to release production material.
Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
Develop and implement data management strategies to ensure data accuracy, security, and accessibility.
Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
Support data analysis efforts to improve silicon performance, yield, and quality.
Ensure compliance with company policies and industry standards related to data security and confidentiality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
Design and build tests to verify that the System on a Chip (SoC) design meets those goals.
Develop and implement advanced technologies for running "benchmark representations" on pre-silicon environments.
Analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The ML, Systems, and Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

We are seeking a talented and motivated R&D Physicist to join our company.

In this role, you will be responsible for designing and carrying out experiments for SiPh chip performance and characterization, performing and analyzing laboratory experiments of chip level optical systems assembly, and developing and managing setups for photonics and laser devices characterization. In this roll you will be required to travel abroad for demonstrations and exhibitions as needed.

Responsibilities:
Design and carry out experiments for SiPh chip performance and characterization.
Perform and analyze laboratory experiments of chip level optical systems assembly.
Develop and manage setups for photonics and laser devices characterization.
Provide technical support to the R&D team for experiments and data analysis.
Contribute to the development of new testing methodologies and techniques.
Ensure adherence to experimental protocols and safety procedures.
Maintain laboratory equipment and supplies.

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.

our company networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute.
We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider our company.
You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.
What you'll be doing:
Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for our next generation of switches.
Learn and understand the switch ASIC across all performance related aspects
Focus on switch hardware modeling.
Analyze and model the communication patterns of key DL, GAI inference and training applications.
Explore innovative ideas to improve and optimize our chip systems performance.

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers

Country:
Israel

City:
Herzliya

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role you will:
Develop and maintain all aspects of the emulation environment- Emulation model, Test plan, Validation environment
The Emulation engineer is involved in validation of significant aspects of ASIC development-chip performance, SW-HW API , system boot and functional flows
Expect to work closely and be part of the development process of the RTL design, verification, software development, testing, and more
Participate in design methodology and tool automation work as needed

The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV). Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops EyeQ SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future company EyeQ SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.

The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV). Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops EyeQ SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future company EyeQ SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats motivated by great technologyand outstanding people. We are leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world!
We are now looking for a CPU Architect in the CPU team! our company needs a passionate engineer who is comfortable in both the hardware and software worlds to help us push the boundaries of CPU and SoC simulation. Todays complex CPU designs rely on detailed functional models to aid in verification, and to support the running of complex workloads for architectural exploration. Such workloads often span CPU and GPU, such as gaming, Deep Learning (DL), autonomous vehicles, and High-Performance Computing (HPC). These models and workloads enable important decisions to be made about future company CPU architectures and allow us to gain confidence in our HW implementations.
What you'll be doing:
Develop cycle-accurate architectural performance and power models for the CPU core of a complex high performance system-on-a-chip.
Use models to analyze architectural tradeoffs related to CPU Performance and Power, identifying performance bottlenecks on deep learning (DL) workloads, high-performance computing (HPC) workloads, as well as industry standard benchmarks like SPECInt and SPECFp.
Propose micro-architectural alternatives that fit within area, timing and power constraints for the design.
Work with the performance verification team to validate the model, and to root cause disconnects between model projections and design (RTL).