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This is an opportunity for you to integrate with end customers in both hands-on and advisory roles to solve technical challenges with various test cell set ups. To work on the bleeding edge of semi-test technology and to sharpen your relationship management skills while developing strategic partnerships that will round out your arsenal of 3rd party vendor provided products that enhance our solutions.



Key Responsibilities

Influence next generation ATE tester and Test Cell product roadmaps
Work directly with leading edge semiconductor companies supporting their efforts to develop Test Cells to enable advanced chip designs to market
Responsible for the mastering of Teradyne Test Cell products, product applications and policies.
Provide expert advice to customers, Sales, FAEs and support staff while working closely with sales/marketing management and test cell staff to ensure that relevant technical information is promptly and accurately communicated
Develop strategic relationships throughout our sales team and customer's key technical decision makers
Work with marketing on technical differentiation and generation of technical proofs for use by the customer team.
Develop, present, and respond to proposals for specific customer requirements
Coordinate, develop and deliver product demonstrations which display the value of our solutions
Works closely with customers to define new test cell opportunities and support existing sustainment activities. Travel requirements could be 25% or greater.
Lead in new product introduction with integration at customer sites with project management, hands-on integration, and training activities.
Support emerging markets, acting as a liaison between customers and the engineering, marketing, and operations teams to help with their product development.
Keep informed and present updates on competitors, industry news and trends, products services, relevant information about legacy, existing, emerging technologies, and the latest product-line development

Help shape how AI data centers are powered. At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in more than 20 countries, and millions of installations worldwide. Solaredge is expanding its innovation into the fast-growing world of AI data-center power infrastructure. Building on our leadership in solar, storage, and power electronics, we are creating a next-generation Power Ecosystem — integrating Solid-State Transformers (SST), Battery Energy Storage Systems (BESS as UPS), and advanced power-conversion platforms designed for the AI era. Join our UPS Data Centers group and play a key role in developing SolarEdge's next generation of high-performance power conversion and backup power solutions for data centers. As a Senior Hardware Design Engineer, you will take ownership of hardware development throughout the entire product lifecycle—from concept and design through validation and mass production—working on complex, multidisciplinary systems in a fast-paced environment. What will you be doing?
* Design and develop advanced power electronics hardware for UPS systems.
* Lead hardware development from concept through mass production, including schematic design, board development, validation, and product release.
* Design analog and power electronic circuits for high-power applications.
* Perform hardware bring-up, debugging, validation, and optimization.
* Plan and execute electrical, thermal, EMI/EMC, and reliability tests to ensure product performance and compliance.
* Collaborate closely with Mechanical, Software, System Engineering, Integration, and Manufacturing teams throughout the development lifecycle.
* Support design reviews, root cause analysis, and continuous product improvements.
* Work with laboratory equipment to evaluate, troubleshoot, and validate hardware designs.
* Contribute to system architecture discussions and technical decision-making.

Country:
Israel

City:
Modiin

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 30 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are seeking an Automated Test Equipment Engineer to join our dynamic team. You will be responsible for the design, development, and implementation of automated test systems for our cutting-edge products. This role requires a strong background in hardware engineering, as well as experience in test automation and system integration. Responsibilities:
* Design and develop hardware solutions for automated test systems, including test fixtures, load boards, and interface circuits.
* Perform hardware debugging, troubleshooting, mass production support and optimization to ensure reliable and efficient test systems.
* Develop and maintain hardware documentation, including schematics, layouts, and mechanical designs.
* Design and develop software for test automation, including test sequencing, data acquisition, and result analysis.
* Collaborate with cross-functional teams, including hardware, software, engineering, quality, and manufacturing.
* Stay up to date with the latest trends and technologies in automated testing procedures.

Country:
Israel

City:
Modiin

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact
Establish and drive DFT verification activities within the SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

We are looking for talented engineers to help us develop a semiconductor platform based on revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. Our Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented physical design implementation engineers to join our excellent Physical Design team, which develops our next generation of products for the cloud market.

Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.

Help shape how AI data centers are powered. At our company, we're a global leader in smart energy technology, with over 3,000 employees, offices in more than 20 countries, and millions of installations worldwide. we are expanding its innovation into the fast-growing world of AI data -center power infrastructure. Building on our leadership in solar, Storage, and power electronics, we are creating a next-generation Power Ecosystem - integrating Solid-State Transformers (SST), Battery Energy Storage Systems (BESS as UPS), and advanced power-conversion platforms designed for the AI era. Join our UPS data Centers group and play a key role in developing our company's next generation of high-performance power conversion and backup power solutions for data centers. As a Senior Hardware Design Engineer, you will take ownership of hardware development throughout the entire product lifecycle-from concept and design through validation and mass production-working on complex, multidisciplinary systems in a fast-paced environment. What will you be doing?
* Design and develop advanced power electronics hardware for UPS systems.
* Lead hardware development from concept through mass production, including schematic design, board development, validation, and product release.
* Design analog and power electronic circuits for high-power applications.
* Perform hardware bring-up, debugging, validation, and optimization.
* Plan and execute electrical, thermal, EMI/EMC, and reliability tests to ensure product performance and compliance.
* Collaborate closely with Mechanical, Software, system Engineering, Integration, and Manufacturing teams throughout the development lifecycle.
* Support design reviews, root cause analysis, and continuous product improvements.
* Work with laboratory equipment to evaluate, troubleshoot, and validate hardware designs.
* Contribute to system architecture discussions and technical decision-making.

Country:
Israel
City:
Modiin

we are looking for a talented Hardware Engineer to join our development team. If you enjoy designing complex electronic boards, solving real-world system challenges, and working on cutting-edge defense technologies, we would love to hear from you.
Responsibilities:

* Design and develop electronic boards and system hardware architecture.
* Lead the full product lifecycle: concept, schematic, layout guidance, bring-up, and production.
* Collaborate with cross-functional teams (software, mechanical, system, and integration).
* Work with subcontractors and support performance analysis.
* Participate in design reviews, system validation, and field testing.
* Support the transition from development to manufacturing.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Staff DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

Required Senior Design Verification Engineer, Networking, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Senior Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

You will guide and mentor our electrical technicians and manage subcontractors, vendors, and suppliers to ensure high-quality, on-time delivery. The role requires deep experience working with EO system electronics, including board-level definitions, mixed-signal design, high speed cameras pipeline, and complex system integration. Your leadership will directly impact on the reliability, performance, and operational capabilities of our tactical EO products.
Responsibilities
Lead end-to-end electrical design of complex EO systems, from concept to validation
Define board-level architecture across analog, digital, power, and high-speed domains
Oversee PCB design and collaborate with external partners and manufacturers
Drive bring-up, debugging, and validation of mixed-signal boards
Perform root-cause analysis and resolve complex electrical issues
Work cross-functionally to ensure seamless system integration
Develop and execute test plans at board and system level
Manage component selection (BOM), vendors, and suppliers
Mentor technicians and support lab activities.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack.
It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development.

As a Senior Design Verification Technical Lead on the Graviton team, you will be responsible for
leading the verification of complex SoC sub-systems, driving cutting-edge verification
methodologies, and ensuring our next-generation Graviton server SoC meets the highest quality
bar before reaching silicon.

What You'll Do:
- Develop and execute verification plans for IO sub-systems- covering interconnect.
protocols, peripheral interfaces, and system-level integration
- Verify IO sub-system features including interconnect protocols, various accelerators engines.
- C embedded SW programing and SW debug skills
- Build and maintain UVM-based verification environments for IO sub-systems.
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
- Contribute to performance verification - ensuring micro-architectural
implementations meet performance targets alongside correctness.

We are seeking algorithms development engineer for electro-optics systems.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.