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which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are looking for a hardware tools Application Engineer who will serve as the primary interface between our internal customers and the development team. our group develops software solutions for various internal teams within the company, and our users include chip designers, algorithm engineers, phy characterization engineers, optics engineers, and more. the role involves not only resolving technical issues but also understanding the broader needs of these engineering teams, contributing new ideas, and helping to design and develop tools that improve their workflow and productivity. 
what youll be doing:
provide Technical Support to internal engineering teams, helping diagnose and resolve issues across diverse areas such as hardware, software, and Linux environments.
debug, solve, and analyze problems effectively, ensuring minimal disruption for engineering workflows.
understand customer needs (chip design, algorithm development, phy and optics characterization, etc.) and translate them into product improvements or new tools.
collaborate closely with software developers to enhance existing solutions and design new internal tools.
communicate findings, solutions, and technical insights effectively to both customers and the development team.
collect, analyze, and summarize customer feedback to drive continuous improvements.

board designer in the hw team is the project leader.
the position consists of product specification, electrical schematics, component selection and layout guidance.
hands-on development and testing in a lab environment, accompanying production and qualification processes.

Power the Future with us!  we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. Are you passionate about designing high-performance power systems that move from concept to mass production? Join us and take a leading role in shaping our next-generation flagship products! What Youll Do:
* Lead the end-to-end development of advanced power electronics hardware - from architecture and schematic design through validation and mass production.
* Own complex board-level designs, driving performance, reliability, and cost optimization.
* Design, simulate, build, TEST, debug, and bring to life robust power solutions under real-world constraints.
* Collaborate in a multidisciplinary R&D environment alongside Mechanical, Software, system, and Certification teams.
* Influence product architecture and technical direction with hands-on engineering excellence.
* Ensure on-time delivery of high-quality, production-ready designs. Why Join Us?
* Work on impactful, market-leading products.
* Be part of a highly collaborative, multidisciplinary engineering culture.
* Take real ownership and influence technical decisions.
* See your designs transition from concept to millions of units in the field.
Country:
Israel
City:
Herzliya

Help shape how AI data centers are powered. At our company, we're a global leader in smart energy technology, with over 3,000 employees, offices in more than 20 countries, and millions of installations worldwide. we are expanding its innovation into the fast-growing world of AI data -center power infrastructure. Building on our leadership in solar, Storage, and power electronics, we are creating a next-generation Power Ecosystem - integrating Solid-State Transformers (SST), Battery Energy Storage Systems (BESS as UPS), and advanced power-conversion platforms designed for the AI era. What will you be doing:
* Taking part in the development of the companys flagship products
* Responsibility for the development from the design stage to the final product, including all tests necessary to deliver the product to mass production (electronic tests, thermal tests, EMI tests).
* Working with other teams inside the Hardware division and outside of it (such as the Mechanical department, Software and more)
Country:
Israel
City:
Modiin

description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent failure analysis practical engineer to join our team and build qms state-of-the-art control and orchestration platform. she or he should be a talented and motivated person, who is a real team player, and which can collaborate closely with other engineers from different disciplines and quantum physicists.
the production site is in migdal haemek ( Flex ).
responsibilities:
yield monitoring and improvement
analyze hw failures to a component level in both digital and analog domains.
identify failure trends
rma process handling
failure reports & closure

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.as a design & power methodology team manager within the server chip design team, you will be responsible of managing and leading design and power methodologies from ip to SOC, pre and post silicon. you will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.you will work closely with cad vendors and internal teams to develop lead design and power methodology and execution.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead flow and methodology development and assimilation across multiple groups. work closely with cad tool providers as well as internal cad teams.
plan, execute, track progress, assure quality, and report status.
work closely with internal customers and support multiple activities and deliverables.
drive design methodologies such as design construction, cdc, rdc, sdc. drive power at: ip and SOC rtl/gate level optimization, estimation, correlation.

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. What will you be doing:
* Taking part in the development of the company’s flagship products
* Responsibility for the development from the design stage to the final product, including all tests necessary to deliver the product to mass production (electronic tests, thermal tests, EMI tests…).
* Working with other teams inside the Hardware division and outside of it (such as the Mechanical department, Software and more)

Country:
Israel

City:
Herzliya

we are hiring a senior pcie firmware to the chip design pcie firmware team. you will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation devices in a wide range of fields - low-level C layer between hw and fws, automation challenges, and Python testing environment.
what youll be doing:
implement fw and verification features in a pre and post silicon environments in the pcie technology
collaborate with other teams in the pcie group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods
improve the existing automated process

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

Our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.

we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams. what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.

we are now looking for an engineering lab technician in the optical assembly team to support developing new nvidia's products. this newest member will collaborate with an innovative multidisciplinary world-class team of engineers to help build and develop our industry leading transceivers. in this role you will run multiple sophisticated assembly platforms, so there will be plenty of opportunity for learning new skills related to the field of advanced packaging. the primary responsibility is to support our engineering teams during development to ensure outstanding quality gpu server products may be released to the market and delight our customers so that ai scientists and datacenter operators can achieve their professional aspirations using nvidia technology. the new lab team member will work independently to complete daily tasks according to priorities, demonstrate a passion towards system level product quality, and should be comfortable in the lab environment.
what youll be doing:
participating in development of new packaging technologies while working tightly with process development team.
prepare and conduct experiments to TEST new assembly technologies and materials.
operation and maintenance of variety of platforms involved in process of packaging - wire bonding/pick&place/active alignment.
maintain laboratory hardware and handle materials.