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This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will be part of a team developing application-specific integrated circuits (asics) used to accelerate networking in data centers. you will have multiple responsibilities in areas such as project definition, design, and implementation. you will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.you will also be responsible for performance analysis for a networking stack using your knowledge.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead an asic subsystem.
understand how it interacts with software and other asic subsystems to implement data center networks.
define hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.

our networking delivers innovative, endtoend infiniband and ethernet connectivity solutions for servers and Storage. our portfolio includes adapter cards, switches, cables, and software designed to maximize datacenter performance with industryleading bandwidth, latency, and scalability. we serve diverse markets including highperformance computing, enterprise, cloud, and web 2.0.
our mission is to stay ahead of the market by delivering groundbreaking technologies that accelerate data and unlock new possibilities. our ethernet solutions are designed for sectors such as media & entertainment and any domain requiring advanced datastream and tcp/ip acceleration.
what youll be doing:
lead a multidisciplinary team of 15+, including mechanical design engineers, draftsmen, mechanical librarians, and lab technicians.
own all sustain engineering activities, including hw bug resolution and ongoing product support.
drive task forces to investigate and resolve production issues, reliability challenges, and failure analyses.
support design teams and take an active part in handson design work.
lead the inspection and approval process for secondsite and secondsource parts and components.
own and continuously improve mechanical department methodologies and working procedures.
maintain and support the cad & plm systems, ensuring best practices and efficient workflows.
manage and mentor the draftsman team and technicians operating the mechanical lab & workshop.

Were looking for a talented Embedded SW Engineer to join our innovative team. As a member of our team, you will be responsible to innovate, design and implement embedded software in C/C++ for our chipset.
Responsibilities
Design, implement and optimize the embedded software driving our chipset (drivers, middleware and application layer)
Collaborate with System architecture and Hardware groups to deliver quality system solutions
Optimize code for memory usage, performance, and power efficiency
Ensure compliance with Safety and Industry standards

we are seeking for a Verification engineer. We are seeking a highly skilled Verification engineer to join a Processor Verification team working on nextgeneration processor cores. In this role, you will take a key part in verifying critical processor blocks, collaborating closely with architecture and design teams to ensure functional correctness. You will own verification activities endtoend from TEST planning and environment development to execution, coverage analysis, and closure- using advanced verification methodologies.

We are looking for a talented and driven Embedded software engineer with strong C / C ++ expertise to join our cutting-edge 5G software development team.
In this role, you will design, implement, TEST, and maintain RF firmware components that power key 5G features in a high-performance, Real-Time environment.
Responsibilities:
Develop Embedded software in C / C ++ for hard real&-time systems.
Design, implement, and maintain hardware-software interfaces for seamless interaction with dedicated hardware components.
Implement 5G feature functionality at the firmware level.
Perform rigorous unit and integration testing to ensure reliability, performance, and robustness.
Participate in debugging, optimization, and continuous improvement of firmware modules.

Designs, develops, troubleshoots and debugs software programs for enhancements and new products. Develops software and tools in support of designs. Analyzes, designs, programs, debugs, and modifies software enhancements and/or new products used in local, networked, cloud-based or Internet-related computer programs. Using current programming language and technologies, writes code, completes development, and performs testing and debugging of applications.

Your Opportunity:
Expertly implements designs using modern programming practices.
Obsessed with quality.
Eager to learn.
Should lead/drive software development initiatives.
Participates in/leads design.
May perform other duties and responsibilities that management may deem necessary from time to time.

Were looking for engineers who are proactive, curious, and take full ownership of their work. In this role, youll have the opportunity to drive real impact, shape the direction of our product, and grow as a technical leader.
You will:
Take end-to-end ownership of features-from design and implementation to deployment and ongoing improvement
Build high-quality, scalable, and resilient systems using modern engineering practices
Work closely with PM, design, and security experts to define and deliver customer-facing experiences
Drive technical direction and make thoughtful tradeoffs that balance speed, quality, and long-term maintainability
Bring a strong sense of initiative-identifying opportunities, raising issues early, and pushing ideas forward
Qualifications
Minimum Qualifications
B.Sc. or M.Sc. in Computer Science, Software Engineering, or equivalent.
3+ years of professional software development experience.
Strong expertise in C/C++ and/or Rust.
Hands-on experience with at least one of:
Windows internals (process model, memory manager, IO manager, registry, drivers/WDF/KMDF)
Linux kernel development (modules, syscalls, device/IO subsystems, scheduling, security models)
Experience with low-level debugging
Solid understanding of networking or security protocols, memory safety, and concurrency primitives.
Ability to independently plan, design, and deliver engineering components in an ambiguous environment.

we are looking for a C++ Developer.
Job Description:
Creating architectures and code for experimental setups in laboratories (at the interfaces between software and hardware).
Developing auxiliary tools for research (automation, running on server farms, tools for data presentation and processing).
Developing HIL (Hardware in the Loop) and SIL (Software in the Loop) physical simulation infrastructures.

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

abra is seeking for an System Engineer This role requires leading the development of advanced EW (Electronic Warfare) systems and suits, including system-level definition, requirements specification, and preparation of technical documentation for various development teams and subcontractors. Additionally, the position includes leading and being responsible for the system engineering of the product throughout all project phases, from writing specifications, system verification and lab integration, delivery to the client, and field testing. Full-time, Sunday–Thursday, Holon, Israel.