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As a Pre-Sales Engineer for SOC Transformation you will be the expert for our Cortex portfolio, a Next-Gen AI-powered security operations platform. You will play a key role in defining technical solutions that secure a customers key business imperatives.
You evangelize our industry leading solutions in Security Intelligence and Automation, XDR, Attack Surface Management, XSOAR, and Incident Response that establish Palo Alto Networks as a customers cybersecurity partner of choice. Additionally, lead CloudSec Transformation with expertise in Posture Management, Cloud Detection & Response, AppSec, and other key areas, ultimately establishing Palo Alto Networks as the cybersecurity partner of choice.
Your Impact
Collaborate with account teams to recommend and develop customer solutions within your assigned specialization area
Present to customers as our expert at all levels in the customer hierarchy, from practitioner to senior leadership
Lead and support customer demonstrations that showcase our unique value proposition
Scope and Lead Proof of Value (PoV) projects for prospective customers based on best practices to ensure technical win in your assigned opportunities
Drive high technical validation and PoV win rates within your assigned specialization area
Architect solutions that will help our customers strengthen and simplify their security posture
Accelerate technical validation of proposed solutions within your specialization
Document High-Level Design and Key Use Cases to ensure proper implementation and value realization of Palo Alto Networks Solutions
Help our customers build and develop further their services around Cortex solutions
Lead conversations about industry trends and emerging changes to the security landscape
Discuss, with credibility, competitive offers in the marketplace and position ours as the best alternative
Assist account solutions consultants to respond effectively to RFIs/RFPs while serving as the main technical point of contact for Cortex
Position Palo Alto Networks or Partner-delivered services as appropriate to ensure proper implementation and value realization of Palo Alto Networks solutions.

As a Senior Product Manager for the XSIAM SIEM team, you will play a critical role in leading a major domain within the Cortex ecosystem. We are seeking a candidate with a leader mindset, someone prepared to take total ownership and responsibility for a critical product area that directly contributes to the global success of XSIAM. In an environment of fierce competition, you will be expected to drive our product strategy by deeply understanding how to deliver superior value within the broader XSIAM platformization vision.
Key Responsibilities
Total Domain Ownership: Lead the end-to-end product lifecycle for a major SIEM pillar. You are responsible for the strategic vision, sequencing scope, and removing blockers to ensure predictable, high-quality delivery.
Platformization & Competitive Value: Drive the shift from siloed legacy tools to a converged security platform. Utilize a Human+AI approach to research competitor strategies, identifying unique value drivers that ensure XSIAM remains the definitive choice for modern SOCs.
Customer & Stakeholder Engagement: Act as a primary liaison to our most significant global customers. You will meet regularly with security leaders and key stakeholders to understand complex operational challenges and translate them into high-impact product innovations.
​​Cross-Functional Collaboration: Serve as the central bridge between peer product teams, engineering, sales, and domain consultants. You will equip global field teams with crisp value narratives to uplift win rates, accelerate market adoption and global go-to-market initiatives.
Advanced AI Roadmap: Own a forward-looking roadmap that integrates agentic AI into the SIEM workflow, ensuring our customers to automate threat detection and response at an unprecedented scale.

As a Senior or Principal Software Engineer in Cortex Cloud, you will contribute to the development and scaling of cloud-native security solutions for enterprise organizations. This role involves working within an established team to evolve a high-traffic product, with a focus on refining architecture, optimizing the technology stack, and maintaining engineering standards.
Your responsibilities include writing reliable code, influencing product direction, and designing distributed systems. You will be expected to make technical decisions that impact the long-term stability and performance of cloud workload protection services.
AI Integration & Engineering Workflow
A core component of our development process is the use of AI. Rather than basic code completion, we integrate AI assistants as functional components of our workflow. Our team utilizes a multi-agent AI system (IDEX/ProDex) that assists across the development lifecycle: from planning and architecture to code analysis and security reviews.
In this role, you will:
Work with AI Tools:Utilize platforms such asGemini, Claude, and Cursorfor tasks beyond code generation, including root-cause analysis, system design reviews, and architectural assessment.
Develop AI-Augmented Workflows:Help refine how AI is integrated into the SDLC, including the orchestration of agents and the development of internal tools that extend AI capabilities across our codebase.
Maintain Quality Standards:While AI assists in increasing velocity, you are responsible for the technical output. This includes critical review of all generated code and ensuring that AI-assisted work aligns with our architectural requirements and security benchmarks.
Interact with Specialized Agents:Coordinate with AI agents (Product, Architecture, Security) that operate on shared context to assist in managing complex engineering tasks.
We are looking for engineers who are interested in leveraging AI as a technical tool to manage complexity and who want to contribute to the practical application of human-AI collaboration in a cloud environment.

Required ASIC Leader
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Review micro-architecture specifications
Supervise verification team members and provide professional guidance
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for an experienced Backend / Graph Database Engineer with experience in Neo4j to join our team.
You will be part of building a large-scale cloud security (CIEM) platform for enterprise customers, where graph-based modeling and computation are at the core of how we analyze identities, permissions, and access paths.
This role combines strong backend engineering with advanced graph thinking - transforming traditional compute-heavy permission analysis into efficient, scalable graph-based solutions.
Your Impact
Take part in the development of a large and complex cloud security (CIEM) platform for enterprise organizations
Design and implement graph-based models to represent identities, permissions, roles, and resource relationships
Build scalable services using Neo4j for real-time and batch graph processing
Optimize complex Cypher queries for performance at scale
Write clean, testable, readable, and maintainable code that performs well for thousands of customers
Design systems that meet high standards of scalability, reliability, and security
Collaborate across teams to define and deliver graph-driven security features.

Required Software Modeling Team Leader
Job Description
Meet the Team
Join the Silicon One team in developing a unified silicon architecture for web-scale, service provider, and enterprise networks. Our silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact:
As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the SiliconOne family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.
In this role, you will:
Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for SiliconOne devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback.

We are hiring for a Principal/ Senior Backend Engineer to join our fast-paced KSPM (Kubernetes Security Posture Management) team in Cortex Cloud, located in our TLV office. Cortex Cloud is Palo Alto Networks' next-generation cloud security solution.
In this role, you'll be key in developing and scaling the core parts of our KSPM solution. Our team's goal is to help Cortex Cloud customers understand and fix security issues in their Kubernetes workloads across all major cloud providers.
The ideal candidates are software engineers with a "can-do" attitude and a passion for solving real customer problems. You should be a person who wishes and is able to work closely with the team and our partners across Cortex Cloud to make decisions and drive features end-to-end.
For us, caring about people is not a slogan; we are looking for individual contributors who enjoy and want to work with great people and collaborate on delivering business value across PANWs vast customer portfolio.
Your Impact
End-to-end backend development of features and core components across the software development life cycle (design, develop, test, deploy, maintain)
As a principal software engineer, independently drive and collaborate with others to deliver high impact features in the KSPM domain
Work with customers and provide solutions to their day-to-day work and challenges
Contribute to team-wide efforts - code reviews, design reviews, technical and architectural decisions.

We are looking for a highly motivated and customer-focused professional. As part of the Tier 3 Cortex XDR support team, you will serve our customer base by providing technical support, by answering incoming support inquiries and managing escalations, phone calls, and emails in an effective, efficient, and friendly manner within defined service level agreements.
Our methodology is first class support. Weve been recognized for it as an industry leader and were dedicated to continuing this standard. In this role, you will work with our technical account managers to personalize our customers experience. You will learn your clients business objectives in and out within their technical environment and focus on mitigating risks and resolving any technical issues in their networks. Youre close to the deployment of cybersecurity solutions - and we need you to recognize risks before they arise. You get a thrill from seeking out complex issues and finding their resolutions - and you dont wait for those issues to escalate from our clients. Instead, you find them. Youll be working hand in hand with our developers to reproduce the issues you find and develop permanent solutions to prevent them in the future.
Key Responsibilities
Respond to customer-reported issues in adherence to established Service Level Agreements
Triage customer reported issues and respond to them via ticketing system, phone, or remote sessions
Perform advanced troubleshooting at the application level and OS level, using your knowledge and relevant expertise
Identify the area of fault (code, environment, or configuration) and work with the appropriate team(s), characterizing and implementing the fix
Provide timely feedback on the development process on customer-reported product problems
Document actions to effectively communicate information internally and to customers
Facilitate root cause investigations and manage the implementation of corrective and preventative measures.

We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team:
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
We are at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact:
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Required PHY Firmware Technical Leader
Meet the Team:
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.