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Our technology has no boundaries! we are building the worlds most groundbreaking and state of the art accelerated compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers.
We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Developing models for simulations and performance testing, analysing the results and development of future HW and SW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are looking for a passionate Firmware Engineer to join our NIC Firmware Core team. You will be joining a team whose primary mission is to work on innovative networking adapters technologies and take the success of the current and next company networking devices to the next level using a wide range of platforms - C layer between HW and FW, C++ OOP verification environment and automation challenges.
What youll be doing:
Take part in the design, development, testing, debugging, and optimization of many angles of the network adapters' core features
Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows
Improve our team methodologies.

we are hiring a senior, hands-on engineer to lead technical innovation in our Design Verification (DV) automation infrastructure. This role requires a strong design/verification background combined with a proactive approach identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. You will directly influence how verification is performed across our companys next-generation Networking chips, enabling more scalable, efficient, and robust flows for complex ASICs powering the AI revolution.
What you'll be doing:
Lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
Identify key challenges and inefficiencies in current DV methodologies and proactively propose and implement improvements.
Work closely with DV engineers, design teams, and tool developers to ensure solutions are practical and impactful.
Balance innovation with hands-on engagement in daily DV issues keeping a strong connection to real-world challenges and support needs.
Act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for DV automation.

We are now looking for a Chip Design Verification Engineer. we are seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company.
What you'll be doing:
Develop shared verification code and solutions to be widely used by the chip design team.
Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.
Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.
Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Collaborate with designers, verification specialists to accomplish your tasks.
Develop training sessions.

we are looking for a creative Senior Power Firmware Architect to lead the shaping of future data centers and networks. In this role, you will play a key role defining the future of our Smart-NIC firmware stack and Switch firmware stack, with emphasis on power related features, collaborating with ASIC architecture/design teams and with software architecture/design teams.
What you'll be doing:
Define strategic vision for our company power saving features together with adjacent power, software and hardware architects.
Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.
Outbound work includes customers engagements, publishing white papers, blogs and conference lectures/BOFs.

We are looking for a Experienced Backend Engineer.
At SubStrata were building a machine learning based software that helps sales and business-development professionals push the deal forward and convert more prospects into clients.
As a full-stack engineer, youll play a key role in our expanding core technology team.

powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, were helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential.
We are seeking an experienced Backend Tech Lead to join our recommendations group. As a Tech Lead, you will be instrumental in shaping the technical direction and architecture of our backend systems. You will leverage your deep expertise in backend technologies to design, build and scale backend services while guiding a group of engineers toward delivering robust, high-performance solutions. This role offers the opportunity to collaborate with cross-functional teams and contribute to projects that impact the entire organization. If you're a leader with a passion for backend development, we would love to have you on board!

As a Backend Tech Lead, your responsibilities will include:
Mentoring and guiding backend engineers to ensure high-quality code and effective development processes.
System design and architecture: Designing scalable, efficient, and secure backend systems, including APIs and data storage solutions, using technologies like Python, MySQL, Redis and Elasticsearch.
Tech stack evolution: Driving improvements in backend technologies, frameworks and development practices.
Cross-functional collaboration: Working closely with product managers, frontend teams and other stakeholders to ensure backend services meet business requirements and technical specifications.
Performance and scalability: Ensuring that our backend services are highly available, scalable and optimized for performance.
Cloud infrastructure: Overseeing cloud services and ensuring backend systems are seamlessly integrated with cloud platforms.
Code quality and best practices: Writing and maintaining clean, maintainable and well-documented code, while fostering a culture of code reviews, continuous improvement and adherence to best practices.
Technical leadership: Owning the technical direction of backend systems, making key architectural decisions and promoting industry best practices within the group.

We are currently seeking a Senior Silicon Security Architect.
we are seeking a technical leader interested in defining, crafting, implementing, and guiding the implementation of security research, architecture, implementation, and design for next-generation our company Networking products. You'll be expected to take a strong hands-on role, working with diverse teams across our company and with external partners to meet security requirements for our state-of-the-art network products.
What you'll be doing:
Research, design, develop and implement architecture solutions (Hardware and software) meeting internal and external security requirements and standards.
Apply innovative hardware security primitives to enable next generation secure software extensions supported by hardware.
Collaborate with partners on the implementation of open-source software.
Collaborate across the company to guide the direction of Silicon security, TEE, working with hardware, software, research and product teams.
Architectural modeling, validation, microarchitectural definition, following standards bodies, and developing infrastructure enabling trusted platforms using hardware security methods.
Work with customers, partners to identify and address security issues and threats.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our companys next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.
What you'll be doing:
Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.
Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
Define the implementation of debug capabilities to support performance validation and improvements
Understand our system requirement and help define the POR of our switch product line.
Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.

Responsibility:
Scope, design, and implement high-performance APIs and services.
Collaborate with engineers and product managers to deliver robust solutions in short development iterations.
Develop maintainable and clean code with heavy reliance on developer testing.
Make thoughtful trade-offs that consider business priorities, user needs, and a sustainable technical foundation.

We are seeking a highly motivated Chip Design Architect to join our team of experts and help shape the future of high-performance computing. Our next-generation Infiniband and NVL switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in industries such as finance and research labs. As a Chip Design Architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation of switches that will be used by top researchers and engineers around the world. The products you'll develop will be integrated in many leading-edge compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.
What you will be doing:
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project.
Define the HW boot, clock and Reset architecture for Switch ASIC
Develop slow-speed interface architecture specifications and design guidelines, conduct trade-off analysis for different architecture options, and oversee the implementation of the chosen architecture by the chip design / FW / SW teams.

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.
our company's networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware features and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.
What you will be doing:
Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system embedded software, user interface and high-level design.
Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.
Define the architecture of implementing physical layer standards into our company's ASIC devices.
Involved in standard bodies activities and definition of next generation protocols.
Define features for the phy layer, to exploit interoperability between different generations of communication.
Be involved in product definition and the high-speed protocols that the our company networking devices will support.
Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.
Become focal point for our ccompanys physical layer networking communication devices.

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.