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Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

You will own the complete EVB hardware bring-up process from initial power‑on through release to internal engineering teams. This role is highly practical and technical, responsible for identifying and resolving complex board- and ASIC-level hardware issues, documenting findings, and driving corrective actions.

Key responsibilities
Own and execute complete EVB hardware bring-up, validation, and qualification activities in the lab.
Perform initial board power‑up, verify power rails and sequencing, validate clocks and resets, and exercise interfaces.
Lead hands‑on debugging and root‑cause analysis of board‑level and ASIC-related hardware failures.
Read and use complex hardware schematics and PCB layout data as primary debugging tools; review PCB manufacturing data when investigating failures.
Perform detailed lab measurements (oscilloscopes, VNAs, logic analyzers, power supplies, electronic loads) and correlate results with schematics, layout, ASIC requirements, and simulations.
Collaborate with SI and PI teams to investigate signal-quality, channel-loss, reflections, power-delivery, and noise issues.
Work with FPGA and BSP/SW engineers during initial system bring-up and debugging.
Document bring-up procedures, debug findings, measurements, known issues, workarounds, and solutions.
Support manufacturing and assembly debug (PCB, SMT, soldering, component and assembly-related failures).
Drive hardware issues through identification, root‑cause analysis, corrective action, implementation, and final validation.

RF system performance prediction and assessment
RF system qualification and validation
Conduct tests as per test plan and analyze test data
Performing technical investigations
Problem assessments and proposal of design solutions
Prepare engineering reports including preliminary observations, data from initial tests, data analysis including any applicable screenshots or data output from test equipment, discussions of proposed solutions, test results of abatement efforts, comparisons of the baseline data with post abatement data and additional recommendations
Prepare engineering test plans, outline test methods, including required test equipment, and anticipated sequence of testing