לוח משרות דרושים Board Design בקיסריה, לחיפוש זה נמצאו 8 משרות

we are seeking a Physical Design Engineer.
Meet the Team:
The Physical Design team owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of most advanced silicon products.
We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.
Your Impact:
You will be part of the team, which is at the heart of software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.
You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Our Board Design Team is growing! Youll collaborate with top industry engineers within the fast-growing Cisco Silicon One group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices-Cisco Silicon One. Our team operates in a startup-like atmosphere within a global, leading corporation.
Our design center is unique, hosting all silicon hardware and software development fields under one roof. Our Networking Chips deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. They are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Your Impact:
Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production.
Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.
Define product specifications, develop electrical schematics, and guide component selection.
Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.

Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.