You will own the complete EVB hardware bring-up process from initial power‑on through release to internal engineering teams. This role is highly practical and technical, responsible for identifying and resolving complex board- and ASIC-level hardware issues, documenting findings, and driving corrective actions.
Key responsibilities
Own and execute complete EVB hardware bring-up, validation, and qualification activities in the lab.
Perform initial board power‑up, verify power rails and sequencing, validate clocks and resets, and exercise interfaces.
Lead hands‑on debugging and root‑cause analysis of board‑level and ASIC-related hardware failures.
Read and use complex hardware schematics and PCB layout data as primary debugging tools; review PCB manufacturing data when investigating failures.
Perform detailed lab measurements (oscilloscopes, VNAs, logic analyzers, power supplies, electronic loads) and correlate results with schematics, layout, ASIC requirements, and simulations.
Collaborate with SI and PI teams to investigate signal-quality, channel-loss, reflections, power-delivery, and noise issues.
Work with FPGA and BSP/SW engineers during initial system bring-up and debugging.
Document bring-up procedures, debug findings, measurements, known issues, workarounds, and solutions.
Support manufacturing and assembly debug (PCB, SMT, soldering, component and assembly-related failures).
Drive hardware issues through identification, root‑cause analysis, corrective action, implementation, and final validation.
Requirements: Bachelors degree in Electrical Engineering or a closely related field.
Minimum 4 years of hands‑on hardware engineering experience focused on board bring‑up and debugging of ASIC/FPGA platforms.
At least 3 years actively performing measurements and analysis. Demonstrated experience using lab equipment (oscilloscope, multimeter, logic analyzer, VNA, power supplies)
Proven ability to read and interpret complex multi‑sheet hardware schematics and correlate schematic signals to PCB layout.
Experience with high‑speed PCB design principles and signal integrity / power integrity troubleshooting on boards with >6 layers or multi‑gigabit interfaces.
This position is open to all candidates.