We're hiring for multiple roles for Logic Design Engineers, and Verification Engineers, on various levels, starting with 3 years of exprience
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture.
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Interact with software developers and system-validation platforms, as part of the verification/validation flow.
Oversee and train junior engineers and take leadership roles on large projects.
Occasional on-call responsibilities for resolving customer issues in production.
Requirements: 3+ years of proven experience in design and/or verification of large ASIC designs
Extensive knowledge of hardware design and verification concepts and tools (e.g., timing, pipelined design, UVM, Specman, unit level and full chip verification, coverage-based verification, formal verification)
A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.
Excellent communication skills in English.
BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.
This position is open to all candidates.