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We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FWinteraction with organization-wide groups.

We are now looking for a Chip Design Manager to join our Network Adapter Silicon group. As a Chip Design Manager in our Networking business unit, you'll join a group of passionate professionals to design, lead the implementation of the next generation state-of-the-art Networking Silicon chips . In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What youll be doing:
Lead a team of design and verification engineers that develops core units within the NIC silicon.
Be responsible for the delivery of complex RTL units and its verification.
Work closely with multiple teams within organizations such as Architecture, Full chip Micro-Architecture, BE, and FW.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Own the special chiplet STA, analyze the timing results, verify correctness and provide budget for the different partitions.

Generate the timing constraints for the STA and the P&R flow.

Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.

Help to shape clock tree, and effect the work of the different teams (Front end, DFT & BE).

Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.

Taking part inflows development.

Take part in ramping up new breaking technologies.

We are looking for an experienced HPC DevOps Engineer to help us build the supercomputers and HPC clusters of the future. As a Senior HPC DevOps Engineer, you'll be a key player in groundbreaking advancements in artificial intelligence and GPU computing. Your expertise will drive the latest breakthroughs, providing insights on at-scale system design and tuning mechanisms for large-scale compute runs. You will work with the latest Accelerated computing and Deep Learning software and hardware platforms, and with many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions. You will interact with HPC, OS, GPU compute, and systems specialist to architect, develop and bring up large scale performance platforms.

What youll be doing:

Innovate and Implement: Design, implement, and maintain large-scale HPC/AI clusters with state-of-the-art monitoring, logging, and alerting systems.

Infrastructure as Code (IaC): Utilize and develop tools to manage infrastructure as code, ensuring scalable and repeatable deployments.

Streamline CI/CD Pipelines: Develop and maintain continuous integration and continuous delivery (CI/CD) pipelines to automate and streamline deployment processes.

Automate Everything: Develop automation scripts and tools to automate deployment, configuration management, and operational monitoring.

Enhance Monitoring: Deploy advanced monitoring solutions for servers, networks, and storage to ensure seamless operations.

Troubleshoot Complex Issues: Perform comprehensive troubleshooting from bare metal to application level, ensuring system reliability and efficiency.

Lead and Educate: Serve as a technical resource, developing and sharing best practices with internal teams.

Drive Innovation: Support R&D activities and engage in proof of concepts (POCs) and proof of values (POVs) for future improvements.

We are looking for a highly qualified chip design engineer with a strong background in ASIC design to join our Chip Design Methodologies & Shared Code team. This team is responsible for developing best in class design methodologies, actively seeking for the best methods to develop design, developing shared code, providing design guidance, and driving the adoption of new technologies. It plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. This role offers a great opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.

As a Principal ASIC Design Methodologies Engineer, you will:

Develop and implement groundbreaking ASIC design methodologies that ensure flawless execution.

Drive exploration and adoption of next-generation tools, techniques, and workflows to meet the evolving demands of advanced semiconductor design.

Lead strategic initiatives aimed at redefining design practices, bringing cutting-edge methodologies to the forefront of the organization.

Collaborate with cross-functional teams to drive ambitious projects from concept to completion.

Influence and mentor other engineers, encouraging a culture of excellence and continuous improvement.

Ensure that the networking chip design team operates with maximum efficiency and the highest possible quality.

We are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at NVIDIA Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

Were looking for a hands-on, tech-driven Software Group Manager to lead the development of Netafims Digital Farming software platforms including our SaaS web applications, mobile apps, and DevOps infrastructure.
Youll manage a cross-functional team of 15 developers (Front-End, Back-End, Mobile) and DevOps engineers, delivering scalable, reliable, and impactful platforms used by thousands of active users worldwide.
This is a unique opportunity to combine deep technical leadership with a purpose-driven mission, building software that empowers farmers to achieve efficiency, profitability, and sustainability through precision agriculture.
Youll help us scale up our software platforms, raise engineering standards, and lead the evolution of our architecture and practices as we grow our global footprint.
What Youll Do:
Lead, mentor, and scale a full-stack development team responsible for cloud-native web and mobile platforms.
Own all stages of the software lifecycle architecture, development, deployment, monitoring, and continuous improvement.
Deliver and maintain SaaS platforms with thousands of active users, ensuring performance, availability, and scale.
Drive platform scalability, modularity, and developer experience to support future growth.
Collaborate with product, UX, agronomy, and hardware teams to create end-to-end digital solutions.
Influence tech decisions and platform evolution, with support from a collaborative leadership team.
Continuously improve engineering processes while building on strong existing foundations.
Set technical direction and drive best practices.

We are looking for a motivated Principal Software Engineer to join our site in Yokneam.
You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.
If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.
Principle duties and responsibilities
Architect, design and develop software for IP/MPLS routers, focusing on routing protocols (e.g., BGP, OSPF, IS-IS) and MPLS (RSVP-TE, LDP, SR-MPLS) functionality.
Design and code quality, scalable, high-performance solutions for embedded systems.
Collaborate with hardware, QA, and product teams to define requirements and validate system performance.
Mentor junior engineers, providing technical guidance and fostering best practices in software development.
Investigate and resolve complex system issues, optimizing for latency, throughput, and reliability.