דרושים » הנדסה » Systems Integration Engineer

We are looking for an experienced Senior System Integration Engineer to join our team.

The role involves planning and executing system integration activities across multiple subsystems, from development through production. You will work with complex systems combining software, computing, IP networks, communications, RF, navigation & control, algorithms, and computer vision.

Responsibilities
System operation and troubleshooting, planning and executing integration processes, writing integration test specifications, preparing performance validation tests, and analyzing system behavior and performance.

We are looking for a Systems Engineer to take ownership of complex multidisciplinary systems from early definition through integration, validation, and field deployment.
In this role, you will bridge hardware, software, algorithms, sensing, and mechanical engineering, ensuring that every part of the system works together to deliver reliable performance in real-world environments. This is a hands-on position that combines technical depth with a broad system perspective, where you will work closely with a small, experienced team to solve challenging engineering problems and drive innovative

Required Power Supply Expert
About the Role
Get a deep understanding and perfect knowledge of the project documentation, especially about the Power Supply system (High Voltage substations, Medium Voltage distribution network, Traction power simulation, Traction and Auxiliary substations) and the interfaced systems: Requirements (MDSM, Owner Requirements, Project Program), Interfaces & integration (NSA), and lists of Deliverables & Tasks (DTG).
Be able to verify the Design that the designers, called Line Managers (LM) will submit, to answer to their questions and to analyze their proposals.
Provide technical, and program feedback and advice on challenges, possible areas of improvement as well as possible alternatives, innovations.
Provide analyses of the LM designs and change proposals to perform Multiple Criteria Analyses to justify decisions for accepting or rejection.
Be able to decide to apply one LM proposal to the other lines for uniformity of the metro network, leading to reduce costs (for construction, integration, operation), to improve operation, make maintenance easier, or to enhance reliability, availability, and safety.
Carry out the studies to change some points of the metro tender documents and manage the LM to apply them.
Coordinate with the other technical disciplines (Rail Systems, CW, external stakeholders) for interfaces and be able to provide all required information for the success of the integration, Testing & Commissioning to get approval on power Supply and lead to the metro operation.
Serve as the Programs technical, process and professional expert on behalf of the Client, to make engineering decisions, accept design proposals or technical solutions, make recommendations, resolve technical clashes, etc., instruct and monitor the implementation and adherence to the Client Metro Network (MN) Power Supply documentation by Metro Line managers/designers and relevant Program participants.
Support, as necessary, the Client in providing technical support in relation to the management of Program statutory approval of designs.
Develop, when needed to be designed/procured at Network Level, the power Supply Programs reference design and/or performance specifications.

Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips.

Responsibilities
Develop robust verification plans for complex digital and mixed-signal optical chip designs.

Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process.

Perform netlist-level simulations with SDF back-annotation for timing-accurate verification

Support FPGA/ASIC bring-up and post-silicon validation as needed

Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.

Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency.

Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers.

Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation.

Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams.

We are looking for some exceptional talent to join our R&D team as a System Engineer.
Your Day to Day:
Translation of Product Requirements to System Requirements
Definition of detailed requirements for sub-systems in a variety of domains (SW, Algo, HW, Electro-optics, Image sensor, Lasers, FW, mechanics, thermal)
Hands-on work with all groups in R&D, Product, PM, Quality, and Operations to ensure compliance with all system requirements
Plan and design system integration test scenarios and V&V process
Research and analysis of system limitations for coming up with the best-performing product
Lead risk management and DFMEA processes

Were looking for a talented Radar System Engineer to join our innovative system team. As a member of our team, you'll work on multidisciplinary system design, which combines cutting edge RF, digital, signal processing, software, hardware and chips development.

Responsibilities
Participate in the development and production of radar sensors.
Debug our Radar ASIC platforms and processors.
Develop subsystem specifications and process flows.
Simulate and validate Radar system performance.
Solve diverse complex problems and help in the debugging and integration process.
Support and manage the product evaluation process involving customers.
Interface with multi-disciplinary product development team in support of design, integration and test of automotive radar systems.
define system requirements for various projects.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

What you'll be doing
Agent architecture: Design the evolution from today's production single-agent system to a multi-agent one: orchestration, task decomposition, runtime and framework choices, and a migration path that does not break what design partners already rely on.
Agent capability: Own the prompts, context, skills, and tool design that make the agent genuinely good at detection engineering across multiple security platforms, not just plausible-sounding.
Evaluation platform: Build the harnesses, judges, and golden datasets that turn "the agent feels better" into a number, plus the CI gates that keep regressions from shipping.
Reliability and safety: Keep long-running agentic sessions healthy in production, and build the isolation and guardrails required of an agent working inside enterprise security environments.
Production debugging: Work real failures from production traces, and turn each one into an eval case that can never regress silently.
Technical direction: Make the calls on architecture, sequencing, and quality bar and be accountable for the outcome, including raising how AI-natively the whole team builds.
Cross-team partnership: Partner with product and customer-facing teams on what the agent should do, and with platform teams on the data and integrations it depends on.

we are looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
A day in the life and how youll make an impact:
Design & Build: Architect and develop electrical modules from concept through production, including PCB design for new systems and continuous improvement of existing ones.
Integrate & Innovate: Bring new components and sensors into our companys product line, working across power supply, communication protocols (I2C, Ethernet, UART), and supporting modules.
Troubleshoot & Lead: Serve as the go-to expert for diagnosing and resolving complex electrical faults - you set the standard for root-cause problem-solving.
Collaborate Cross-Functionally: Partner closely with systems engineers, mechanical engineers, and software teams to shape next-generation features and products from the ground up.
Own Vendor Relationships: Manage subcontractor relationships for end-to-end module delivery, ensuring quality and timelines stay on track.

We are looking for a hands-on FPGA Design Engineer, specialized in high-performance digital design and FPGA-based system development, as part of the QM-Platform team.
This role involves ownership of FPGA interfaces and connectivity logic, including high-speed communication blocks, platform integration, and close collaboration with embedded and hardware teams. You will work on complex FPGA/SoC platforms, enabling robust and scalable solutions for control systems.
Responsibilities:
Own the design and implementation of FPGA-based interfaces such as PCIe, I2C, SPI, and high-speed GT communication.
Develop and integrate FPGA logic on advanced platforms, including Xilinx UltraScale+ and Versal.
Collaborate closely with embedded, hardware, and system teams to ensure seamless HW/SW/FPGA integration.
Drive FPGA bring-up, debugging, and validation at both lab and system levels.
Participate in system architecture definition and cross-team design decisions.