דרושים » תוכנה » AI Workflow Engineer - System Architecture

Required Staff GPU Verification Engineer
Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the world's most widely deployed GPU architecture - Mali. As a Staff Hardware Verification Engineer, you will play a key technical role in verifying advanced GPU components and subsystems, working alongside architects, designers and verification engineers to deliver high-quality, industry-leading graphics technology. You'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
Responsibilities:
Develop and execute verification plans for advanced GPU components and subsystems.
Develop and maintain AI tools, agents, and skills to support our engineering teams and workflows.
Build, maintain and enhance robust verification environments using SystemVerilog and UVM.
Apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
Debug complex functional issues and work closely with Design and Architecture teams to identify and resolve root causes.
Contribute to block-level and system-level verification, including environment integration and regression analysis.
Improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
Participate in verification reviews and support verification sign-off activities.
Share technical knowledge and collaborate with colleagues across the wider GPU engineering organisation.

We are looking for somone to join our WiFi hardware team.
Our team operates in an AI-driven environment where we leverage cutting-edge AI tools to enhance productivity, code quality, and reduce development timelines. You'll be expected to actively utilize and promote AI-assisted development practices within the team.
What you'll do:
In this role, you will work on defining, developing and debugging validation environments for TIs wireless MCU products targeted at Industrial markets. You'll Deep dive into both low level and system level modules, ensure compliance with specifications, collaborate with experienced software, Architecture, design and verification teams and build your skills through hands-on projects and dedicated mentorship.

In this role, as Senior Team Leader of the AI NPU Simulator, you will lead a Group developing a major part of AI simulation framework, in the core of our AI software offering. The AI NPU simulator enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company.

You will drive the development of robust, scalable, and efficient simulation software, working closely with global Architecture, VLSI, and Software teams to shape next generation of AI solutions.

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading software teams, and a track record of delivering complex, state-of-the-art products on time and with high quality. The ideal candidate is execution-driven, innovative, and passionate about building high-performing teams and cutting-edge AI technology.



Responsibilities

Manage and lead two teams (Development + Validation) .

Be accountable for the simulation lifecycle, including architecture, development, validation, and release.

Lead development of advanced simulation models for AI processors.

Own delivery of complex, multi-release roadmaps.

Ensure strong alignment between hardware design, compiler behavior, and simulation models.

Drive system-level correctness and performance accuracy.

Support system bring-up, debugging, and customer-facing activities when needed

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

Our Networking BU group is seeking to hire an expert Firmware Design Engineer for the Ethernet Switch Firmware Core team. The next generation of Switches are a crucial component of the most innovative AI and Cloud Computing Networks in the world. As a member of the Ethernet Firmware Team, you will craft and develop the firmware abstraction layer in the ETH Switch. This role will require you to participate in the design & development of firmware while working closely with hardware and architecture team to ensure timely delivery of our products to the market.

What you'll be doing:

Highly involved in the entire software development process from architecture to integration testing of firmware for the Spectrum ASIC product line.

Work with HW & ASIC team to provide insights into developing the next gen of the groundbreaking of silicon and systems.

Design and implement algorithms to improve system scale and performance.

Work with higher layer software teams to debug issues reported by customers (internal and external).

Design, implement and integrate new features according to the product roadmap.

Have a new insight on how to improve our software? Why not! Bring your ideas to life by innovating during our hackathons

Collaborate with other R&D teams around the globe.

As a senior compiler engineer, you will own the design and development of open source based toolchain and graph compiler. You will drive technical solutions end-to-end, deliver compiler capabilities across all hardware targets, and help mentor engineers. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for engineers who champion this approach.

Responsibilities:

Design and develop open source based toolchain targeting custom DSP and NPU architectures.

Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation.

Champion AI-agentic development practices - integrating AI coding agents into day-to-day engineering workflows.

Own complex components end-to-end, from architecture and design through implementation and delivery.

Provide technical guidance and mentorship to engineers; conduct code reviews.

Collaborate with hardware architecture, algorithms, and software teams globally.

Analyze and optimize toolchain output for performance and correctness across processor families.

Lead a team of compiler engineers responsible for open source based toolchain and graph compiler. You will be a hands-on team leader - driving architecture decisions, guiding engineers, and delivering compiler capabilities across all hardware targets. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for a leader who champions this approach.

Responsibilities

Lead development of open source based toolchain targeting custom DSP and NPU architectures. Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation. Champion AI-agentic development practices within the team - integrating AI coding agents into day-to-day engineering workflows. Mentor engineers and conduct code reviews; build a high-quality engineering culture. Collaborate with hardware architecture, algorithms, and software teams globally. Own team planning, prioritization, and on-time delivery of toolchain features. Contribute hands-on to design, implementation, and performance tuning in C++ and Python.

A leading technology company providing cloud-based customer experience solutions is looking for a Backend Engineer to join its engineering team. This is a 6-month temporary position (maternity leave replacement) focused on building scalable backend systems, developing high-impact features, and leveraging AI-assisted development tools, especially Claude Code, as part of the daily engineering workflow.
Responsibilities:
Develop backend features using Java, Spring Boot and Microservices architecture.
Use AI coding tools for planning, development, code review, and improving engineering workflows.
Design technical solutions, build REST APIs, and work with relational databases.
Participate in architecture discussions, code reviews, and Agile/Scrum processes.
Promote best practices for validating and improving AI-generated code.

We are seeking a Director of Software Architecture to lead and accelerate the evolution of next-generation AI data center and networking technologies. This role is designed for a hands-on, execution-driven leader who pushes boundaries, translates vision into reality, and delivers high-impact solutions at scale. You will operate at the intersection of innovation, architecture, and delivery-shaping the future of AI networking and infrastructure.

What you will be doing:
Drive identification, evaluation, and rapid adoption of emerging technologies, ensuring strong alignment with strategic roadmap and measurable business outcomes.
Lead the design and delivery of advanced networking applications, leveraging data plane programming and modern networking protocols to solve complex, large-scale challenges.
Architect solutions across AI data center environments, integrating GPU-based systems, hardware acceleration, and high-performance networking.
Act as a thought leader and industry influencer-engaging directly with customers, publishing technical content, and representing us at key conferences and forums.
Define and execute a bold architectural vision for our networking in close collaboration with cross-functional software and hardware leaders.

In this role, you will be a key contributor to the design and implementation of AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.

You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of NPU embedded solutions, actively promoting AI capabilities to the customers.

What will you do:

Own and design key components of the AI Graph Compiler software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.