דרושים » הנדסה » Compiler Engineer

As a quantum researcher, your main role will be to develop algorithmic and error-reduction tools to help our partners and customers achieve quantum advantage for their applications. You will develop our companys error reduction methods, including mitigation and correction, and apply them to different use cases by optimizing existing methods, developing new algorithms, and adapting these tools to the realities of running on quantum hardware. This includes taking into account application requirements, noise characteristics, device constraints, and performance on real quantum devices.
Responsibilities
Developing new error reduction methods, including mitigation and correction, for quantum algorithms.
Optimizing error reduction methods for different algorithms, applications, and hardware settings.
Developing new quantum algorithms to enhance performance on real quantum hardware with error mitigation.
Conducting research on applications of quantum computing with our companys partners, including implementing and running proof-of-concept demonstrations of these applications on real quantum hardware. 

Required Senior Software Engineer, CPU, Cloud
About the job
In this role, you will work at the center of our most strategic infrastructure investments. You will join a high-impact team operating on the critical path of our hardware and software evolution, bridging the gap between compute infrastructure and the massive scale of our software stack. You will be responsible for defining the methods and technologies required to model, simulate, and analyze complex hardware systems, with a core focus on security, performance, and correctness analytics, ensuring the efficiency of our future compute platforms. As a software engineer in this group, you will act as an architect, designer, and coder taking ownership of your goal and working in close partnership with cross-functional teams to make it a reality.
You will be at the intersection of hardware design and software optimization for our next-generation high-performance compute cores. You will not just support existing infrastructure; but will be helping build the foundation of our future hardware. Because this work is on the "most critical path" for our future, you will have visibility into and influence over the core technology that powers our most intensive services. You will bridge the gap between silicon-level security research and massive-scale software implementation, working with experimental AI tools that are shaping how we verify and optimize future hardware. You will be building the foundation of our future hardware.
Responsibilities
Drive performance modeling and analysis for next-generation CPUs, while identifying architectural bottlenecks, ensure system correctness, and implement optimization strategies across hardware-software stack to maximize efficiency for compute workloads.
Design, develop, and maintain software modeling tools and simulation environments, leverage C++, Python, and AI-driven methodologies to perform studies and automate analytical workflows.
Conduct security analysis and threat modeling for hardware-software interfaces, while developing and implementing methodologies for detecting, mitigating, and analyzing side-channel and micro-architectural vulnerabilities, ensuring systems meet safety and privacy.
Explore, deploy, and scale experimental AI-driven tooling to automate verification workflows, enhance predictive modeling, and accelerate development cycles, actively contribute to expanding the team's suite of AI-assisted capabilities.
Provide technical leadership in system integration projects, guide cross-functional teams to resolve large-scale compute bottlenecks, influence architectural designs, and facilitate the successful deployment of hardware-software solutions.

Required Micro-Architect
Description
A global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of the company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

Our Network Architecture, Modeling and Performance Insights group is seeking a skilled and driven hands-on Network Modeling Architect to conduct advanced network research and optimization while utilizing and enhancing our advanced simulation tools.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end-to-end performance. You will develop expertise in our simulation tools and write code daily to contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance. If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

 

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generation of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Write production-quality C++ and Python code daily. Hands-on modeling of advanced network topologies, configurations and traffic patterns representing real life AI workloads, and analyze their effect on the system's performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end to end performance. You will develop expertise in our simulation tools and contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance.

If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generations of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Implement modeling of advanced network topologies, configurations and traffic patterns which represent real life AI workloads, and analyze their effect on the systems performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

Were currently seeking a Senior Developer Technology Engineer, Artificial Intelligence. Would you enjoy researching parallel algorithms to accelerate AI workloads on advanced computer architectures? Do you find it rewarding to identify and eliminate system bottlenecks to achieve the best possible performance on pioneering computer hardware? Could you be thrilled about an opportunity to partner with the developer community, working at the forefront of technology breakthroughs that contribute to the success of an industry leader like us? If so, the Developer Technology Team invites you to consider this role.

What you will be doing:

In this position, you will research and develop techniques to GPU accelerate workloads in deep learning, machine learning or other AI domains.

Work directly with other technical experts in their fields (industry and academia) to perform in-depth analysis and optimization of complex AI and HPC algorithms to ensure optimal AI solutions on modern CPU and GPU architectures.

Publish and/or present discovered optimization techniques in developer blogs or relevant conferences to engage and educate the developer community.

Influence the design of next-generation hardware architectures, software, and programming models in collaboration with research, hardware, system software, libraries, and tools for our teams.

The Networking Advanced Development Software team develops new groundbreaking technologies to enable new market shares for the company and tighten customer relationships. These are emerging technologies in networking and distributed computing for the booming AI factories and data centers. They span areas such as AI neural networks, Deep Learning, High Performance Computing (HPC), Storage, Cloud, SW Defined Network, Network Function Virtualization, 5G NR and more. We develop the solutions top-down, all the way from application behavioral analysis, to architecture definition and down to the implementation, using the world-leading our devices. The development traverses any needed component - application SW, middleware SW, OS kernel subsystems, device drivers, embedded SW (Firmware) and CUDA GPU. We collaborate with partners and key customers in the analysis processes and engage with open source communities introducing our leading features.

What youll be doing:

Lead a team of 5 engineers in the advanced technologies development.

Design and implement solutions throughout all layers from high level application, OS and driver subsystem to firmware.

Work on impactful projects involving state-of-the-art high-performance computing hardware and software.

Provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology.

Collaborate with our partners and customers.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for an experienced Firmware Engineer to join the QoS NIC Firmware team at the Yokneam or Tel-Aviv site. You will take part in leading a major development team in our Firmware group while taking part hands-on with development activities. The Firmware team develops cutting edge networking features. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Take part in research, design, and development of QoS and FW algorithms, enhancing performance, reliability, and scalability.

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC Firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.