Requirements:
Bachelors or Masters degree in Computer Engineering, Electrical Engineering, or Computer Science.
7+ years experience in the Linux Kernel architecture, OS Internals and subsystems (Memory Management, IO, Storage, Networking)
Experience and Deep understanding of PCIe standard, topologies and its applications.
Very good understanding of HW architecture and high bandwidth applications.
Strong experience in Performance Analysis and Debugging techniques.
Experience with HW architectures (MIPS & RISCV) and their implementation in the operating system is a big advantage.
Experience in the user space is a good advantage.

Requirements:
Requirements
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.

QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
Requirements
Four or more years of experience in one or more of the following roles in the memory cluster of an Out of Order CPUs:
Architecture or micro-architecture definition.
Performance modeling and studies.
RTL implementation.
Verification of Multithreading.
Education: Academic degree in Computer Engineering or Computer Science

Advantages:
Knowledge and experience in memory ordering architecture.
HW or SW Experience in inter-thread synchronization.
Knowledge of the arm Instruction Set Architecture.

Skills
Good verbal English skills.
Good interpersonal skills.
Team player.

Requirements:
Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks).
3+ years of experience in one or more of following disciplines: development of simulators/emulators for CPUs, definition of CPU features, HW/SW co-design, Low level performance profiling and optimization of SW with exposure to CPU ISA.
Fluent spoken and written English.
Behavioral skills: Team player. Interpersonal skills needed to collaborate with colleagues towards achieving a technical goal.

Advantageous qualifications:
Experience in SW/HW codesign or in definition of new instructions will be a great advantage.
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.).
Familiarity with Vector Architectures.