Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

Youll be joining the post silicon validation team in PHY system group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

We are looking for a Full-Chip verification & Integration Engineer to join our FullChip Switch Silicon team. As part of NVIDIAs Networking business unit, you will work alongside passionate and highly skilled engineers building the next generation of state-of-the-art switch silicon chips. This is a unique opportunity to grow in a technically rich environment and gain broad system-level exposure, and contribute to cutting-edge devices that deliver world-class bandwidth, throughput, and latency.

In this role, you will help integrate and validate complex full-chip flows at the system level, working across multiple engineering domains and learning how advanced silicon products come together from architecture to execution.

What you'll be doing:

Work in a Full Chip verification team that is responsible to integrate and verify our Switch products at system level.

Work closely with multiple teams within the organizations such as Architecture, u-arch, Firmware and all switch units and Ips.

Play a key role in validating the most complex end-to-end chip flows, gaining hands-on experience with system behavior, cross-block interactions, and real product-level scenarios.

Use modern AI-powered engineering tools and automation techniques as part of your day-to-day development and debug workflow.

Learn from experienced engineers in a collaborative environment that encourages technical growth, ownership, and continuous improvement.

Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.

Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

Required Silicon Validation and Debug Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Contribute to developing and improving post-silicon test content that exercises both IP and SoC levels workloads and other compute-intensive scenarios.
Collaborate with architecture, design, and firmware teams to define comprehensive validation plans for SoC features, focusing on power consumption, thermal management, sensors behavior, and performance metrics.
Work closely with design and firmware teams to propose and implement solutions for optimizing SoC power efficiency and performance, including tuning core-to-memory latencies and bandwidth, power control loops, thermal control loops, etc.
Develop and maintain automated test scripts and frameworks (primarily in Python) to improve validation efficiency and coverage.
Participate in early silicon bring-up and platform bring-up activities, ensuring the stability and functionality of high-power multi-core SoCs.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.
Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a talented and experienced Firmware Architect to join our Network Adapter Firmware team in Yokneam.

As part of our technical leadership team, you will define the firmware architecture for next-generation networking devices and drive design of innovative technologies powering the world biggest AI Platforms, cloud computing, HPC, storage, and automotive platforms.

The Network Firmware team develops cutting-edge firmware that enables the world's largest cloud providers and enterprises to deliver high-performance, reliable, and secure networking solutions. Working alongside exceptional engineers across the globe, you'll thrive in a dynamic, collaborative, and fast-paced environment while solving some of the industry's most challenging technical problems.

What you'll be doing:
Collaborate closely with Hardware, Software, and System Architecture teams to define end-to-end solutions.
Define the firmware architecture for new products and features at the core of our NIC firmware.
Lead the design and implementation of strategic technologies, including functional safety, security, and next-generation networking capabilities.
Mentor and technically guide R&D engineers throughout architecture, design, and implementation.
Drive technical direction across multiple teams while ensuring scalable, maintainable, and high-quality firmware architecture.