דרושים » הנדסה » Director of Licensing

We are seeking a technical leader to define, craft, implement, and guide firmware architecture for reliability, availability, serviceability, and power management across next-generation Networking products and platforms. You will take a strong hands-on role, working with hardware, firmware, software, validation, customer engineering, and external partners to build robust, diagnosable, power-efficient systems for large-scale deployments.

What you'll be doing:

Define platform-level firmware architecture for RAS and power management across SoCs, accelerators, DPUs, servers, embedded systems, and data center platforms.

Own error detection, classification, containment, recovery, escalation, and reporting architecture.

Define firmware architecture for power sequencing, power states, reset flows, thermal and power fault handling, idle management, and recovery from power-related failures.

Create firmware specifications for hardware error handling, health monitoring, crash capture, telemetry, diagnostics, debug data, and field serviceability.

Define interfaces and contracts between firmware, hardware, operating systems, BMCs, management controllers, platform software, and cloud/service infrastructure.

Drive architecture reviews, tradeoff discussions, failure-mode analysis, validation strategy, and long-term RAS and power management roadmap planning.

Establish standards for error logs, event schemas, telemetry flows, recovery policies, service diagnostics, and production debug infrastructure.

Guide engineering teams through implementation, validation, silicon bring-up, platform integration, and production deployment of RAS and power management features.

Analyze customer and field failures, identify architectural gaps, and feed lessons learned into future platform designs.

We are looking for an Infrastructure Team Leader to lead and manage a highly skilled team of 4-5 engineers, responsible for Emulation, CAD, DevOps, compute infrastructure, and automation.
This role combines 50% hands‑on and 50% manageiral technical leadership and end‑to‑end ownership of infrastructure, tooling, and release flows.
The position has a significant impact on productivity, quality, and time‑to‑market of the companys silicon products and is reporting directly to the director of the department.
Responsibilities
Lead and mentor the Infrastructure team, including CAD, DevOps, automation, and emulation activities.
Own the definition, development, and maintenance of infrastructure: Emulation, design flows, verification flows, releases, automation, TFS Azure DevOps and CI/CD pipelines.
Drive continuous improvement of infrastructure reliability, performance, scalability, and usability.
Take end‑to‑end responsibility, cross BU, cross site VLSI releases, environments, and production readiness.
Collaborate closely with different stakeholders in the HW and SW RnD teams to align infrastructure with project needs.

This is a high-impact technical leadership role designed for a "star" engineer who can own the entire hardware lifecycle. You will be responsible for stabilizing products from the first prototype through mass production, defining validation strategies, and managing the technical deployment of test stations at global Contract Manufacturers (CMs). You will bridge the gap between R&D, manufacturing, and field reliability to ensure world-class product quality.
Core Responsibilities
Outsourced Station & Vendor Management: Lead the design, setup, and qualification and scale-up of test stations (ICT/JTAG/FT) and debug infrastructure at CM/Outsource partners.
End-to-End Product Stabilization: Own the hardware stabilization process from the first build unit through ramp-up and transition to high-volume production.
Validation & Automation Strategy: Build comprehensive validation plans, review hardware designs for testability (DFT), and integrate automated software tests into production lines.
Advanced System Debugging: Develop hardware debug tools and methodologies to perform deep-dive failure analysis and root cause investigations on systemic issues.
Yield & Data Intelligence: Monitor and optimize yield performance using data analysis techniques to identify trends and failure modes during the NPI lifecycle.
Field & RMA Ownership: Lead technical investigations into field-deployed systems, analyzing diagnostics and telemetry to evaluate RMA claims and provide actionable engineering recommendations.
Cross-Functional Leadership: Collaborate with Mechanical NPI, Test Development, R&D, and manufacturing partners to align test requirements with business needs.
Statistical Process Control (SPC) Implementation: Establish and monitor SPC for critical manufacturing parameters to identify process "drifts" before they result in actual product failures.
Root Cause Corrective Action (RCCA): Lead the formal RCCA process for any manufacturing escapes, ensuring that the "fix" is implemented both in the hardware design and the test software.
Vendor Quality Engineering (VQE): Act as the technical quality lead for CMs and outsourced station builders, defining the "Golden Unit" standards and qualification protocols for all production lines.

We are looking for an excellent Firmware Design Engineer for NVIDIA FW PHY Group. The person will closely work with NVIDIA FW development, architecture, chip design teams and gain deep understanding of NVIDIA's Networking products and technologies. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best chip design team in the industry!

What youll be doing:

Working on the most Ground breaking technology for building AI infrastructure.

Design and develop PHY-layer firmware for our latest networking devices, improving performance and reliability in our next-generation products.

Enabling new SerDes and physical linkup flows.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.

We are seeking a highly skilled and motivated Electrical Validation (EV) Team and System Testing / ATE Team Leader to join our team. This position is crucial in supporting the design, development, and implementation of Automated Test Equipment (ATE) and production test systems.
The Electrical Validation team Lead manages the electrical validation function across our company hardware platforms. This role owns the validation strategy, methodology, lab infrastructure, and execution across all high-speed and control interfaces. The manager ensures robust electrical performance from early prototypes through production release and drives cross-functional alignment between design, SI, firmware, and manufacturing.
The role involves close collaboration with the HW R&D team, Quality, DevOps, and Contract Manufacturing (CM) teams to ensure the delivery of high-quality, reliable products.
This group is part of the HW R&D group.
Key Responsibilities
Define the electrical validation strategy for our company hardware platforms.
Own validation methodology for: High-speed Ethernet (100M-1600G), PCIe Gen1 to Gen5+, SerDes architectures (NRZ/PAM4), Control and management buses (I2C, SPI, RS-232, MDIO, etc.)
Establish structured validation plans aligned with hardware release milestones.
Build and manage a high-performance validation team.
Define lab architecture, including: Equipment selection (oscilloscopes, BERTs, analyzers), Compliance platforms, Automation frameworks, Signal integrity validation environments
Drive early engagement with board design and SI teams to ensure design-for-validation.
Oversee: Compliance (IEEE, PCI-SIG, OIF), Interoperability testing, Stress and margin testing
Lead root cause analysis of electrical failures and systemic issues.
Support NPI, manufacturing bring-up, and yield improvement.
Develop automation and scalable validation methodologies.
Define validation documentation standards and sign-off criteria.
Collaborate with system architecture and software teams to ensure HW-SW integration robustness.
Manage external labs and certification processes where required.
Drive continuous improvement of validation coverage and efficiency.
Lead the full ATE development lifecycle from requirements definition to execution in production, including GUI design and Python scripting.
Develop and maintain boundary scan applications using JTAG Technologies.
Define and maintain test fixtures, including JIGs/Bed-of-Nails, etc., in collaboration with mechanical vendors.
Implement full test traceability systems for production yield and stability monitoring.
Collaborate with R&D and Quality teams to drive product quality and reliability improvements.
Provide onsite support at CM sites, including station setup, installation, training, maintenance, and debugging.
Perform in-depth failure analysis and troubleshooting at the system and component level.
Utilize and maintain a range of test equipment, including:
Work with various communication protocols: TCP/IP, Telnet, SSH, HTTP, SNMP, SFTP, SCP, FTP, RS232, GPIB, I2C, and NI-VISA.
Support testing of embedded systems running on Linux platforms.

We are seeking a highly skilled and motivated Electrical Validation (EV) and System Testing Engineer to join our team. This position is crucial in supporting the design, development and full testing.
The Electrical Validation team Lead manages the electrical validation function across our company hardware platforms. This role owns the validation strategy, methodology, lab infrastructure, and execution across all high-speed and control interfaces. The manager ensures robust electrical performance from early prototypes through production release and drives cross-functional alignment between design, SI, firmware, and manufacturing.
The role involves close collaboration with the HW R&D team, Quality, DevOps, and Contract Manufacturing (CM) teams to ensure the delivery of high-quality, reliable products.
This group is part of the HW R&D group.
Key Responsibilities
Define the electrical validation strategy for our company hardware platforms.
Own validation methodology for: High-speed Ethernet (100M-1600G), PCIe Gen1 to Gen5+, SerDes architectures (NRZ/PAM4), Control and management buses (I2C, SPI, RS-232, MDIO, etc.)
Build and manage a high-performance validation team.
Define lab architecture, including: Equipment selection (oscilloscopes, BERTs, analyzers), Compliance platforms, Automation frameworks, Signal integrity validation environments
Drive early engagement with board design and SI teams to ensure design-for-validation.
Oversee: Compliance (IEEE, PCI-SIG, OIF), Interoperability testing, Stress and margin testing
Lead root cause analysis of electrical failures and systemic issues.
Define validation documentation standards and sign-off criteria.
Implement full test traceability systems for production yield and stability monitoring.
Collaborate with R&D and Quality teams to drive product quality and reliability improvements.
Utilize and maintain a range of test equipment, including:
Work with various communication protocols: TCP/IP, Telnet, SSH, HTTP, SNMP, SFTP, SCP, FTP, RS232, GPIB, I2C, and NI-VISA.
Support testing of embedded systems running on Linux platforms.

We are looking for a highly skilled Advanced Development Engineer to join the Software Architecture Team. In this hands-on role, you will shape the future of large‑scale data centers through advanced simulation, high‑scale telemetry, and next‑generation infrastructure solutions. You will work at the frontier of technology - exploring, prototyping, and proving new concepts - and turn them into scalable, production‑ready foundations. Your work will span large‑scale telemetry pipelines, data integrity at extreme scale, and advanced simulation frameworks used to model, validate, and optimize complex data‑center environments.

As part of the Architecture team, you will directly influence cross‑company platforms and long‑term technology direction, while actively contributing code, frameworks, and ideas. You will also have opportunities to participate in and contribute to open‑source projects and communities.

What you'll be doing:

Discover, evaluate, and prototype emerging technologies with a strong focus on simulation, scale, and system behavior modeling.

Design, implement, and evolve high‑scale software systems integrated across the full Data Center life‑cycle.

Build advanced simulation solutions to model data‑center behavior, telemetry flows, failure scenarios, and system performance at scale.

Define and expand large‑scale telemetry and observability pipelines, ensuring accuracy, consistency, and traceability of data.

Incorporate new and diverse data sources to continuously extend the capabilities of a centralized, petabyte‑scale Data Lake.

Collaborate closely with engineering, architecture, and research teams across us to translate business and technical requirements into robust, scalable solutions.

Work side‑by‑side with architects and data scientists to design, validate, and evolve data and simulation architectures.

Contribute to defining the architecture of next‑generation monitoring, analytics, and simulation platforms for hyperscale data centers.

Extend existing platforms and actively contribute code, designs, and leadership to Open Source projects and communities.

Our work in Networking and AI is transforming the world's largest industries and profoundly impacting society. Our Networking product security team is looking for an outstanding technical AI red teamer with hands-on safety and security experience to help us improve the safety posture of AI models, systems and infrastructure. In this role you will reduce risk, threats, and vulnerabilities in our networking AI products.

What you'll be doing:
Drive hands-on safety and security research on a range of AI and networking products.
Develop tools and processes to expose novel weaknesses in AI models and systems to preempt threats.
Participate in defining and ensuring AI development processes meet safety and security standards.
Partner with cross-functional teams to understand needs and implement solutions.
Be a technical focal point across multiple teams and provide hands-on AI safety, security and engineering expertise.

We are seeking an experienced Security Architect who has experience in confidential computing and attestation systems. The ideal candidate should have deep expertise in at least one leading confidential compute architecture and ideally in PCIe support around TDISP, IDE, SPDM. Strong knowledge of general system security, virtualization and hardware-enforced isolation primitives is essential.

What you'll be doing:
Lead, research, design, develop, and implement solutions for next-generation confidential computing network devices.
Develop novel hardware isolation mechanisms to provide defense in depth in the SoC.
Collaborate with external and internal hardware and software teams to implement and deliver the architecture.
Architectural modeling, validation, microarchitectural definition, and developing proofs-of-concept for secure platforms.

We are looking for a motivated Principal FPGA Engineer to join our team in Raanana.
You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.
If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.
Principle duties and responsibilities :
Design and develop FPGA/ASIC solutions across the full product lifecycle, including feasibility studies, architecture definition, implementation, verification, and production support
Work independently to deliver high-quality engineering solutions with minimal supervision.
Operate at the system architecture level across multiple design domains.
Serve as a Subject Matter Expert (SME) in one or more technical areas and provide consulting to other teams.
Lead and contribute to complex, high-impact projects critical to the business.
Integrate AI tools in FPGA/ASIC development process.
Mentor and provide technical guidance to junior and senior engineers.