דרושים » סטודנטים » Chip Design Student

We are looking for talented student to help us develop the semiconductor platform which is based on revolutionary architecture.
Take part in the development of products within disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest Cloud provider, within a dynamic, open, and fast-paced environment.

We are looking for talented students to join the Verification team and help us technically lead the challenges of the next decade.

We are looking to hire Embedded Software Engineering Students to join the SW group and take a major part in redefining the future of our cloud.

The Graviton SW team is looking for an Embedded Engineering Intern to join us in building next generation platforms. At the platforms team, you'll work on large and complex
boards, helping bring our Silicon devices into the fleet. You'll have the opportunity to learn about next gen platforms and contribute to the technologies that power the world's largest Cloud provider.

To Apply: Please submit your CV together with your updated grade sheet compressed into one pdf. Only applications with CVs & grades will be considered. Without both the CV and grades, we cannot consider your application.

we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - its an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.



Key Responsibilities


Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent

we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.



Key Responsibilities

Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
Work closely with the verification team to run simulations, analyze results, and ensure design quality
Interact with Architecture and Backend teams to understand the full chip development lifecycle
Help leverage AI-based automation tools to optimize engineering workflows

Required Post Si Student position
Our EPG (EyeQ Platform Group) is responsible for the entire lifecycle of the EyeQ chip, from design to validation across different product segments.
In this role, you will work with our engineers across multiple teams to analyze, debug, and develop automation solutions, as well as execute validation plans. You will join the lab team within the Post-Si group and take responsibility for a variety of activities required to validate our EyeQ products. This includes supporting team activities, maintaining platform HW, OS & tools, executing manual and automated tests, and screening/debugging failures. You will also be expected to collect information, analyze data, and provide summary reports.