דרושים » חשמל ואלקטרוניקה » Senior ASIC Physical Design CAD Engineer

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Location: Caesarea and Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Requirements:
Minimum Qualifications
A VLSI Design Engineer with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevent background.
5+ years of hands-on experience in a relevant domain
Strong understanding of Place & Route flow
Preferred Qualifications
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
Requirements:
Minimum Qualifications:
A VLSI Design Engineer with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background.
2+ years of hands-on experience in a relevant domain
Strong understanding of Place & Route flow
Preferred Qualifications:
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
Silicon One is seeking a Physical Design Group Leader.
Meet the Team
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
Requirements:
Minimum Qualifications
A VLSI Design with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.
10+ years of hands-on experience in a relevant domain
4+ years of proven Management or Technical Leadership experience.
Preferred Qualifications
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
We are seeking a Physical Design Technical Leader.
Meet the Team
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
Requirements:
Minimum Requirements
A VLSI Design with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.
7+ years of hands-on experience in a relevant domain
Preferred/Advantageous Qualifications
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time and Hybrid work
Required PHY Post Silicon Validation Engineer
Job Description
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Silicon One group as part of the silicon development.
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Who You'll Work With
You'll be part of our Group driving our game changing next generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.
Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!
Requirements:
Minimum Requirements:
B.Sc/ M.Sc in Electrical engineer / Computer Science
Experience with C++/C#, Python
Knowledge in post-silicon validation or automation for networking systems specifically for DSP-based silicon systems, including debugging, validation, and optimization of DSP architectures.
Preferred Qualifications:
Knowledge in communication and signal processing
Knowledge in Linux, Git, Data Bases
Knowledge in development of GUI
experience with Jenkins Devops environment
System orientation with multi-disciplinary approach and multitasking capabilities.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
Required ASIC Design Engineer - Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.
Requirements:
Minimum Qualifications
B.Sc./M.Sc. in Electrical Engineering from a top university
3+ years of experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
10/05/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time and Hybrid work
Required ASIC Design Engineering Technical Leader
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Silicon One is transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8659417
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
Required PHY System
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Requirements:
Minimum Qualifications:
Education: B.Sc/M.Sc in Electrical Engineering or Computer Science from a top university.
3+ years of relevant experience required
System Orientation: Strong multi-disciplinary approach with multitasking capabilities.
Major Advantage: Specialization in Communication and Signal Processing.
Experience: Hands-on experience with lab work is advantageous.
Technical Skills: Proficiency in C++, Python, and Matlab is a plus.
Preferred Qualifications:
Varies based on the team and business needs
Preferred Qualifications are desired education E
Experience, and skills that are in addition to Minimum Qualifications.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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דיווח על תוכן לא הולם או מפלה
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תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
Required PHY System Technical Leader
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Requirements:
Minimum Qualifications:
B.Sc/M.Sc in Electrical Engineering or Computer Science from a top university.
7+ or more years of relevant experience required
System Orientation: Strong multi-disciplinary approach with multitasking capabilities.
Major Advantage: Specialization in Communication and Signal Processing.
Experience: Hands-on experience with lab work is advantageous.
Technical Skills: Proficiency in C++, Python, and Matlab is a plus.
Preferred Qualifications:
Varies based on the team and business needs
Preferred Qualifications are desired education E
Experience, and skills that are in addition to Minimum Qualifications.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
Required PHY Firmware Technical Leader
Meet the Team
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices
Requirements:
Minimum Qualifications:
B.Sc. or M.Sc. in Electrical Engineering or Computer Science from a top university
8+ years of relevant experience in system and firmware.
Strong system-oriented mindset with a multi-disciplinary approach
Ability to work on complex problems while multitasking across domains
Preferred Qualifications:
Experience with C++, Python.
Familiarity with processor architecture
Experience working in cross-functional, fast-paced development environments.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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