דרושים » הנדסה » Senior PCIe Firmware Engineer

We are hiring a Senior PCIe Firmware to the Chip Design PCIe Firmware team. You will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation our devices in a wide range of fields - low-level C layer between HW and FWs, automation challenges, and Python testing environment.

What youll be doing:

implement FW and verification features in a pre and post silicon environments in the PCIe technology.

Collaborate with other teams in the PCIe group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods.

Improve the existing automated process.

We are looking for a skilled Software Developer with strong hardware knowledge to join our diverse team passionate about developing low-level software and test infrastructure for our networking and Interconnect products. As a technical focal point, you will work at the intersection of hardware and software, taking ownership of driver development, hardware bring-up, and test system architecture. You will be instrumental in driving innovation by developing low-level software that directly controls hardware, debugging sophisticated hardware-software interactions, and creating robust testing solutions. If you're passionate about code development, automation, innovation, reading schematics, debugging hardware with software tools, and becoming a key technical contributor, we'd love to have you on board!


What You'll Be Doing:

Collaborate with multi-functional teams including hardware, electrical, thermal, and mechanical engineers to understand hardware specifications and develop corresponding test requirements.

Take the lead in debugging hardware-software integration issues using instruments, and software tools to pinpoint root causes.

Develop low-level drivers in C/C++ for hardware components and build DLL wrappers for integration with higher-level C# applications.

Review and interpret hardware schematics and datasheets to understand signal flows, timing requirements, and implement appropriate software control mechanisms.

Lead all aspects of hardware bring-up, validation, and deployment of test solutions to production environments, ensuring accurate integration.

We are seeking an experienced and highly motivated Firmware Engineer to join our NIC/Switch Firmware Development Team in Tel Aviv.

The successful candidate will design and develop innovative firmware features to unleash the full potential of our ConnectX/Switch architecture.
Our Firmware Team develops cutting-edge networking features for cloud, HPC, and storage.

This position requires a broad background in NIC or Switch architecture, along with a proven ability to develop robust and efficient solutions to complex design challenges.

The Firmware Team drives the data growth of the worlds largest companies. With talented engineers around the globe, our work environment is dynamic and meaningful.

What You Will Be Doing:
Deepen Your Expertise: Gain a thorough understanding of system debugging, networking technology and stacks, as well as the HW/FW/SW relationships.
Innovate Firmware Features: Design and implement new firmware features in our NIC/Switch Firmware core (e.g., our ConnectX/Spectrum products).
Optimize Performance: Characterize and refine key firmware design elements and code to maximize performance and ensure robustness and flexibility.
Learn Complex Project Management: Understand how a large, complex software project is operated, maintained, qualified, and released, and learn how hardware and firmware are developed.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs.

This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:
Develop and maintain simulation components for the physical layer of our high-performance networking chips (e.g., GPUs, switches, NVLink, Ethernet...).
Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex physical-layer behaviors in software.
Define, implement, and validate simulations of features such as link training, error injection, and transceiver behavior, making the simulation platform a go-to internal platform for development and debugging.
Extend and optimize the simulation infrastructure by contributing to CI pipelines, automated test frameworks, and regression tools.
Support internal users by debugging simulation flows and collaborating on bug resolution.
Take part in future-facing innovation by enabling simulation for next-generation devices and features.

We are looking for a Senior networking test engineer with strong system‑level debugging skills to join our End‑to‑End Verification team. You will work on cutting‑edge Ethernet‑based AI clusters, owning complex issues across hardware, system software and AI workloads. We are widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

What youll be doing:

Design and review test and product requirements across the Ethernet / NIC / DPU / Switch portfolio, focusing on large‑scale AI cluster behavior.

Build and maintain realistic customer‑like testbeds, including heterogeneous hardware, OS / driver combinations and complex network fabrics.

Own end‑to‑end cluster troubleshooting: reproduce customer scenarios, triage across the stack and drive issues to root cause and fix.

Read and understand relevant source code to identify defects, validate fixes and improve logging and instrumentation.

Collaborate closely with development teams to debug NCCL, RoCE/RDMA and related networking components using logs, code inspection and targeted experiments.

Define tests and guide the automation team to implement robust suites that produce actionable logs, metrics and traces.

Run Regression, Performance, Functional and Scale testing, analyze results and provide clear, data‑driven reports to stakeholders.

Profile and benchmark deep learning training and inference workloads, correlating model‑level metrics with system and network telemetry to uncover bottlenecks.

We are looking for a skilled Software Developer with strong hardware knowledge to join our diverse team passionate about developing low-level software and test infrastructure for NVIDIA's networking and Interconnect products. As a technical focal point, you will work at the intersection of hardware and software, taking ownership of driver development, hardware bring-up, and test system architecture. You will be instrumental in driving innovation by developing low-level software that directly controls hardware, debugging sophisticated hardware-software interactions, and creating robust testing solutions. If you're passionate about code development, automation, innovation, reading schematics, debugging hardware with software tools, and becoming a key technical contributor, we'd love to have you on board!

What You'll Be Doing:

Collaborate with multi-functional teams including hardware, electrical, thermal, and mechanical engineers to understand hardware specifications and develop corresponding test requirements.

Take the lead in debugging hardware-software integration issues using instruments, and software tools to pinpoint root causes.

Develop low-level drivers in C/C++ for hardware components and build DLL wrappers for integration with higher-level C# applications.

Review and interpret hardware schematics and datasheets to understand signal flows, timing requirements, and implement appropriate software control mechanisms.

Lead all aspects of hardware bring-up, validation, and deployment of test solutions to production environments, ensuring accurate integration.

The Networking Advanced Development Software team develops new groundbreaking technologies to enable new market shares for the company and tighten customer relationships. These are emerging technologies in networking and distributed computing for the booming AI factories and data centers. They span areas such as AI neural networks, Deep Learning, High Performance Computing (HPC), Storage, Cloud, SW Defined Network, Network Function Virtualization and more. We develop the solutions top-down, all the way from application behavioral analysis, to architecture definition and down to the implementation, using the world-leading our devices. The development traverses any needed component - application SW, middleware SW, OS kernel subsystems, device drivers, embedded SW (Firmware) and CUDA GPU. We collaborate with partners and key customers in the analysis processes and engage with open source communities introducing our leading features.

What youll be doing:

Design and implement solutions throughout all layers from high level application, OS and driver subsystem to firmware.

Work on impactful projects involving state-of-the-art high-performance computing hardware and software.

Provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology.

Collaborate with our partners and customers.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, Register-Transfer Level (RTL) coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for test (dft) etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.