דרושים » חשמל ואלקטרוניקה » Senior Chip Design Engineer, Port IP Group

Requirements:
What we need to see:

Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate, or equivalent experience.

2+ years of experience in RTL verification.

Self-motivated, ability to work independently and drive tasks to completion.

A team player with good communication and interpersonal skills.

Ways to stand out from the crowd:

Knowledge in Specman, Verilog.

Background in Networking.

Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate, or equivalent experience.
2+ years of experience in RTL verification
Self-motivated, ability to work independently and drive tasks to completion
A team player with good communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman, Verilog
Background in Networking.

Requirements:
B.Sc. in Electrical Engineering or Computer Engineering with high scores or equivalent experience.
1+ years of experience in RTL design and/or dynamic verification.
Completion of programming and logic design courses.
A great teammate with good communication and interpersonal skills.

Requirements:
B.Sc. in Electrical Engineering or Computer Engineering.
5+ years of experience in RTL design or RTL verification.
Previous experience in networking - an advantage.
A team player with good communication and interpersonal skills.

Requirements:
B.SC./ M.SC. in Computer Engineering/ Electrical Engineering/ Communication Engineering or equivalent experience
2+ years experience in verification or similar position
High Level of English
Ability to work as part of a team
Ways to stand out from the crowd:
Validated experience in Verification
Experience in Specman
Background in UVM/SV
Knowledge in HDL (Verilog/VHDL).

Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
6+ years of managerial experience in a chip design or verification domain.
10+ overall years of experience in RTL design/dynamic verification.
Knowledge in network protocols and/or HPC and distributed calculations - advantage.
A team player with good communication and interpersonal skills.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
6+ years of relevant experience
Great teammate.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

5+ years of experience in physical design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.

Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
8+ years of experience in dynamic verification.
Knowledge in network protocols and/or HPC and distributed calculations - advantage.
A team player with good communication and interpersonal skills.