our company has transformed computer graphics, PC gaming, and accelerated computing for over 25 years. Its a unique legacy of innovation fueled by great technology-and amazing people.
Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU and Networking products act as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. Looking into the future, power management and power optimizations present a huge challenge in the development of silicon throughout all the development life cycles. Together, we can meet the challenge. Join the team and see how you can make a lasting impact on the world. The networking architecture team seeks a highly-skilled, leading engineer to explore, define and assimilate power optimization methods across all design disciplines.
What you'll be doing:
You'll be responsible for developing architectures, algorithms, models, and methodologies aimed to improve the power consumption of our DPU and NIC products.
Play a key role in facing these challenges and lead the research of innovative power techniques and power modeling that will drive our solutions to the next level.
Take an active part in HW design reviews.
Requirements: Bachelor or Master (advantage) degree in science fields from a known institute
At least 3 years of experience or equivalent in computer architecture such as performance analysis, power management, power optimization and characterization, power modelling, etc.
Strong EE fundamentals, knowledgeable in digital design, frontend, and backend practices, power analysis, and characterization.
High-level programming (SystemC or C++) and scripting (Python) skills is considered an advantage.
Exceptional analysis skills. Excellent problem-solving, teamwork, and interpersonal skills.
This position is open to all candidates.