דרושים » חשמל ואלקטרוניקה » Senior VLSI Verification engineer

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Responsibilities

Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing ASICs used to accelerate networking in data centers. You will have dynamic, multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

We operate in true startup mode: fast-paced, ambitious, and deeply technical. The project is challenging across architecture, RTL, verification, and schedule and we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.

We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Required CPU Verification Engineer
Description
Develops innovative hardware and software for AWS cloud customers.
Annapurna Labs is like a big start-up. We develop cutting-edge technologies, work with amazingly talented engineers, and truly shape the future.
Working for Annapurna Labs is thrilling, fast-paced, and a constant learning experience.
Annapurna Labs is looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.

We are looking for talented engineers to help us develop a semiconductor platform based on revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. our Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented physical design implementation engineers to join our excellent Physical Design team, which develops our next generation of products for the cloud market.
Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.
A day in the life
Your day will be filled with dynamic technical challenges that push the boundaries of semiconductor design. You'll collaborate with cross-functional teams, diving deep into intricate physical design processes, and translating complex architectural concepts into tangible technological solutions. Expect to engage in cutting-edge problem-solving that requires both creative thinking and precise technical execution.

looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.

You will work alongside other talented engineers to develop our cutting-edge AI chips.

If you are motivated and skilled in VLSI and excited about AI, we want to meet you!

Responsibilities
Bring architecture requirements of AI Chips to power and area-efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with the backend and DFT to converge the design into silicon.
Join the bring-up of the features with SW when silicon is back in the lab and the magic happens.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in our company infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

we are looking for a Senior Logic Design Engineer to join the ride as we spearhead the next revolution in electronics and lead the IP Integration Enablement.
Responsibilities

Customer-Centric Integration Leadership

Act as the voice of the customer in internal R&D reviews, advocating for integration simplicity, design compatibility, and customer usability.
Identify and address integration challenges early in the development cycle to ensure seamless adoption by customer design teams.
Integration Infrastructure & Collateral

Define and oversee all integration-related deliverables, ensuring quality, consistency, and alignment with customer integration needs.
Review and contribute to the development of collateral, including:
o Lint, CDC, RDC and IPXACT views

o Register maps, ICL and PDL files

o Simulation and emulation views

o Integration testbenches and verification collaterals

Out-of-the-Box Integration Benchmark & Regression

Develop and maintain an out-of-the-box environment to evaluate IP integration from the customers perspective.
Validate end-to-end IP Integration in representative SoC contexts using the Proteus IP integration flow as described in the integration guide.
Develop and maintain integration regression tests to ensure integration KPIs are consistently met.
Cross-Functional Collaboration

Train and mentor Application Engineers on the Proteus IP integration playbook, ensuring consistent and effective deployment across customer projects.
Provide expert support for complex integration challenges escalated through the field teams.
Gather structured feedback from Application Engineers and customers to continuously refine integration methodologies and improve the overall integration experience.