דרושים » הנדסה » Formal Verification Engineer

As a Formal Verification Engineer, you'll play a crucial role in ensuring the quality and reliability of our Graviton product line. You'll own the complete verification lifecycle, from planning through execution, collaborating with cross-functional teams to deliver quality results in a fast-paced environment.

Key job responsibilities:
Drive formal verification efforts for complex hardware designs.
Develop comprehensive verification plans and execute them independently.
Collaborate with design, system and verification teams.
Identify and resolve design issues using formal methods.
Contribute to methodology improvements and best practices.

Our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

We are seeking for System Validation Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms.

As a System Validation Engineer at Annapurna Labs, you'll be at the forefront of developing advanced technologies that power the world's largest cloud platform. Your expertise will be critical in ensuring the reliability, performance, and quality of next-generation cloud solutions that support hundreds of thousands of businesses globally.

Key job responsibilities:
- Design, implement, and execute comprehensive test plans and test cases.
- Develop and maintain sophisticated automated test frameworks.
- Identify, document, and track software and system defects with precision.
- Continuously review and enhance quality assurance processes.
- Collaborate closely with development teams to ensure exceptional product quality.

Our DDR SoC team is looking for an experienced verification engineer to be involved in the development of our current and future SoC.
Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
Verify the SoC DDR interface including the integration of advanced DDR controller and PHY.
Build block level Verification of the DDR interface
VIP integration for interface protocols and DDR.
Collaborate with designers, architects and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Write and debug tests that combine UVM methodology and SW code.
Define, develop, and execute complex verification scenarios on the DDR interface.

Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.

We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
As a SIP engineer, you will be involved in:
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.
Hands-on lab work involving oscilloscopes, spectrum analyzers, and other RF/mixed-signal measurement equipment, for advanced electrical characterization.

You will undergo a comprehensive training program, providing you with the essential knowledge and skills required to succeed in this field. The work is multidisciplinary, bridging physical design, electromagnetic theory, and practical engineering challenges.

We are looking for a Senior Software Engineer with experience in networking and software, to join the networking SW group. We are looking for a candidate with the ability to thrive in an environment with complex software and hardware designs, who can take ownership, and lead the development of key SW components for our network cards.

You will take part in developing, integrating, and deploying networking technologies, starting from the identification and definition of project requirements, feature development, deployment and operational support, on a very large scale.
As part of your role you will join a team of engineers who are developing software implementing AWS RDMA technology, for Machine Learning and High Performance Computing (HPC) customers.
Your code will run on millions of servers worldwide, as part of the Nitro system. Not many software engineers in the world have the opportunity to create code that runs at such a large scale.
The role includes working closely with HW, FW, and SW teams all over the world.