דרושים » חשמל ואלקטרוניקה » Experienced DFT Engineer

Our Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Our Automated Driving group in Haifa is looking for a Junior DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.

At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

We are looking for a talented and driven VLSI CAD Automation & DevOps Engineer to join our team. This role combines expertise in front-end automation, continuous integration, CAD tooling, and full-stack development to support and enhance our VLSI verification workflows.
What will your job look like:
Flow & CI/CD Automation
Automate RTL lint, CDC/RDC, synthesis checks (front‑end only), and UVM regression flows.
Build and maintain CI/CD pipelines (Jenkins/GitLab CI) for simulation, coverage collection, and sign‑off checks.
Implement pre‑submit checks (lint, CDC) and nightly regressions with dashboards for pass/fail and coverage metrics.
EDA Tooling & CAD Enablement
Manage and integrate front‑end EDA tools (e.g., VCS, Xcelium, Questa, SpyGlass).Develop scripts to parse logs/reports (lint, CDC, coverage, simulation) and generate actionable summaries.
Maintain PDK-independent front‑end tool configurations and flow reproducibility.
Compute & Licensing
Operate and optimize compute farm schedulers (LSF/SLURM/Grid Engine) for simulation and regression jobs.
Monitor and tune license usage for front‑end tools (FlexLM/Lmx), ensuring high availability and efficiency.
Observability & Support
Build dashboards for regression health, coverage trends, and farm/license utilization.
Troubleshoot flow failures, triage environment vs. design issues, and publish runbooks for common problems.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.