Quality and Reliability SoC Engineer

לפני 14 שעות

Quality and Reliability SoC Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

We are seeking an experienced and driven Quality and Reliability (Q&R) Engineer to own and manage the qualification and long-term reliability of advanced automotive semiconductor products. In this role, you will be responsible for defining, executing, and ensuring product compliance with industry standards (e.g., AEC-Q100, JEDEC, ISO26262), collaborating cross-functionally with design, test, packaging, and manufacturing teams to ensure robust quality performance throughout the product lifecycle.
What your job will look like:
Lead end-to-end quality and reliability activities for new automotive product introductions (NPI), including definition of Q&R plans, stress test strategy, and execution of qualification.
Define and align qualification strategy with AEC-Q100, JEDEC (JESD22), and customer-specific requirements.
Drive reliability risk assessments (FMEA, FMEDA, fault tree analysis) in collaboration with functional safety and design teams.
Manage product qualification timelines, budgets, and documentation, including reliability test reports, risk mitigation plans, and deviation justifications.
Interface with OSATs and test/assembly partners to ensure reliability test execution, including HTOL, ELFR, HAST, PTC, HTSL, and solder joint reliability.
Lead root cause analysis and corrective actions for product or qualification-related failures (FA/8D process).
Act as the Q&R voice in cross-functional reviews (DFX, tape-out, production ramp, and PCN).
Track field returns, drive reliability monitoring, and contribute to continuous improvement activities.
Support audits, customer quality inquiries, and product certifications as needed.

Requirements:
B.Sc./M.Sc. in Electrical Engineering, Materials Science, Physics, or related technical field.
5+ years of experience in semiconductor quality/reliability, preferably in automotive-grade ICs or modules.
Strong knowledge of AEC-Q100, JEDEC standards (e.g., JESD47, JESD22), and automotive PPAP/APQP process.
Hands-on experience with reliability testing, failure analysis techniques, and qualification management.
Familiarity with packaging-related reliability (FCBGA, FCCSP, WLCSP, QFN) and stress mechanisms (solder fatigue, moisture sensitivity, ESD/LU).
Proven ability to work across multidisciplinary teams (design, test, process, FA, packaging).
Excellent communication, organizational, and problem-solving skills.
Experience with radar, vision, or ADAS automotive products- Advantage.

This position is open to all candidates.

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8316199

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לפני 12 שעות

FA Engineer with X-Ray -Inspection Expertise

חברה חסויה

Location: Haifa

Job Type: Full Time

we are seeking a skilled Failure Analysis (FA) Engineer with expertise in X-ray inspection techniques to join our AV Platform team. The ideal candidate will specialize in using advanced X-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability
What will your job look like?
Perform detailed failure analysis using X-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
Interpret and analyze X-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
Develop and optimize X-ray inspection procedures and protocols for failure analysis and quality control.
Prepare test specimens: cutting, mounting, grinding, polishing and chemical etching
Collaborate with product engineering, quality assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
Prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
Support reliability testing and failure mode analysis for new and existing products.

Requirements:
Bachelors or Masters degree in Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or related field.
Proven experience in failure analysis with a strong focus on X-ray imaging and inspection.
Proficiency in operating and interpreting data from X-ray inspection systems (e.g., 2D/3D X-ray CT).
Strong analytical and problem-solving skills with attention to detail.
Familiarity with semiconductor, electronics, or other relevant industry standards.
Excellent communication skills for reporting technical findings clearly and effectively.
Ability to work independently and as part of a cross-functional team.
Experience with complementary failure analysis tools e.g., SEM, FIB and optical microscopy.

This position is open to all candidates.

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8316628

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לפני 15 שעות

SoC Verification Technical Lead

חברה חסויה

Location: Haifa

Job Type: Full Time

Which department will you join? The SOC verification group owns the important and challenging job of verifying our company's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Requirements:
BSc in electrical engineering, computer engineering or computer science
10+ years of experience working in verification environment, tests, and test bench development (C/C++/SV)
TestPlan defining and Coverage-Driven Verification experience
Fullchip/SOC verification experience, strong system understanding
3rd-party IPs integration testing experience
Waveform debugging with the latest EDA tools, root-cause bugs independently
Knowledge in Industry Standard protocols such as AXI/OCP/APB
SW embedded experience, C/C++ skills - Advantage
Strong skills in scripting Perl/Python - Advantage
System Verilog writing skills, preferably in OVM/UVM Advantage.

This position is open to all candidates.

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8315971

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לפני 10 שעות

Experienced DFT Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Requirements:
Proven Experience in either SCAN or MBIST tools and flows
At least 2 years of DFT experience in both SCAN/MBIST
At least 5 years of experience in the ASIC/SoC industry
Knowledge of Hierarchical SCAN methodology
Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows
Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG)
Knowledge in Automotive industry FuSa (Functional Safety)
Knowledge of Synthesis flows
Proven skills in Perl / Python / TCL
Excellent communication skills
BSEE/MSEE is required
If you are an experienced DFT engineer, seeking to learn, improve and to be challenged by new concepts and complexities in relation to DFT for Automotive - your place is with us!

This position is open to all candidates.

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8316790

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לפני 11 שעות

Experienced SoC Design Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

our company's Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Requirements:
BSc/MSc in Electrical/Computer engineering
Proven Experience in either SCAN or MBIST tools and flows
At least 5 years of experience in the ASIC/SoC industry
Proven skills in Perl / Python / TCL
Knowledge of Hierarchical SCAN methodology
Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows
Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG)
Knowledge in Automotive industry FuSa (Functional Safety)
Knowledge of Synthesis flows
DFT experience in both SCAN/MBIST - Advantage.

This position is open to all candidates.

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8316738

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לפני 13 שעות

Physical Design Sub Full Chip / IP Layout Lead

חברה חסויה

Location: Haifa

Job Type: Full Time

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years of experience in IP or Full Chip Integration & Physical Verification on complex IPs or SoCs.
Expert knowledge in P&R & signoff methodologies.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).
Team player with excellent communication skills, customer orientation, and a can-do attitude.

This position is open to all candidates.

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8316347

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לפני 9 שעות

Electrical Validation & Embedded SW Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

our companys Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles. In our company, Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, and CDPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a relatively small team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our companys EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions, and automation, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

Requirements:
BSc or MSc in Electrical or Computer engineering
3+ years of hands-on experience in validation or HW/SW debug, including the use of advanced lab equipment (Scope, BERT, etc.)
Hands-on experience with test automation development or FW development or automated data analysis
Strong debugging and advanced analysis experience
Experience in Signal/Power Integrity design- An advantage
Experience with analog circuits or PHY IP knowledge - An advantage
Strong sense of ownership, commitment, and responsibility
Good interpersonal communication skills.

This position is open to all candidates.

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8316821

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12/08/2025

Senior/Staff RTL Design Engineer

חברה חסויה

Location: Hod Hasharon and Haifa

Job Type: Full Time

As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.

Responsibilities:

Understanding the high-level specification and requirements of functional units of micro-controller and application processor products.

Define the Micro-architecture for an unit and developing its RTL, including all design stages.

Collaborate with verification team on the test plan development for the blocks and verification closure.

Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets.

Requirements:
An ideal candidate will have at least 10 years of work experience in RTL design, SoC integration, memory controller and interconnect IP design.

Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Minimum Skills and Experience:

Experience with memory sub systems and bus architecture.

Required Skills and Experience :

BS/MS in Electrical and/or Computer Engineering with over 10 years of experience.

Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus.

Experience with Verilog, coupled with design synthesis targeted to achieve specified frequency, power, and area targets.

Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.

Great communication & teamwork skills.

This position is open to all candidates.

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8300242

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לפני 14 שעות

Senior Electrical Validation & Embedded SW Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

Requirements:
BSc or MSc in Electrical or Computer engineering
7+ years of hands-on experience in validation or HW/SW debug, including the use of advanced lab equipment (Scope, BERT, etc.)
Hands-on experience with test automation development or FW development or automated data analysis
Strong debugging and advanced analysis experience
Experience in Signal/Power Integrity design- An advantage
Experience with analog circuits or PHY IP knowledge - An advantage
Strong sense of ownership, commitment, and responsibility
Good interpersonal communication skills.

This position is open to all candidates.

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8316095

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לפני 10 שעות

Experienced Physical Design Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence. We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
3+ years experience in the physical design field.
Experience in scripting languages like Tcl/python/Perl/tcsh.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Experience in relevant domains - Advantage.
Building or maintaining implementation tools and flow Advantage.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8316767

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לפני 13 שעות

Physical Design Sub Full Chip / IP Timing Lead

חברה חסויה

Location: Haifa

Job Type: Full Time

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years of experience in IP or Full Chip or IP level STA on complex SoCs.
Expert knowledge in timing closure & signoff methodologies.
Experience with DFT architecture, Async timing concepts & verification.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).
Team player with excellent communication skills, customer orientation, and a can-do attitude.

This position is open to all candidates.

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