דרושים » מדעים מדוייקים » Verification Engineer

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Responsibilities

Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the worlds most widely deployed GPU architecture Mali. As a Principal Verification Lead Engineer, youll guide the technical direction for complex GPU verification programs, mentor talented engineers, and influence methodologies that set the standard for our next-generation graphics processors. Your work will make a visible impact across multiple projects, ensuring that our technology continues to deliver outstanding performance and quality for millions of users worldwide.

What Youll Do:
Define and lead verification strategies for sophisticated GPU systems.
Shape and evolve verification methods and frameworks to improve coverage, scalability, and efficiency.
Anticipate challenges and design practical, forward-thinking solutions that help multiple teams succeed.
Lead the Technical Vision:
Take full ownership of end-to-end verificationplanning, execution, and deliveryfor advanced GPU components and subsystems.
Apply advanced techniques such as coverage-driven, random, and formal verification.
Be responsible for verification reviews, sign-offs, and integration of block-level and system-level environments.
Collaborate and Influence
Act as the primary technical contact across Architecture, Design, and Product teams.
Coach and mentor engineers, helping them grow their skills and confidence.
Chip in to continuous improvement in our verification tools, flows, and CI systems.
Innovate with Purpose:
Bring creativity and technical excellence to how we verify hardware.
Drive automation and efficiency through scripting and next-generation verification tools.
Represent our leadership in verification internally and externally.

Are you ready to make a significant impact by tackling SW verification challenges? We are seeking an exceptional candidate to work with world-class technologies in the domains of High-Speed Communication and Virtualization for our most advanced markets and customers. Our products encompass Ethernet and InfiniBand protocols, delivering a wide range of cutting-edge networking, storage, and security services for cloud, complex compute, and AI workloads. As a Software Verification Engineer, you will play a crucial role in ensuring on-time and high-quality releases.

What Youll Be Doing:

Take an active part in development, integration, and verification with R&D.

Develop and maintain test automation frameworks and scripts using Python.

Identify, analyze, and report software defects, inconsistencies, and other quality issues.

Drive design verification flows and methodologies improvements.

Perform functional, integration, and regression of software applications and networking protocols.

Work with planning and tracking systems to manage the release progress and build release indicators.

Participate in code reviews, provide feedback, and suggest improvements to enhance the quality and maintainability of the software.

Continuously monitor and evaluate the effectiveness of test processes and methodologies, recommending improvements as necessary.

Stay up to date with industry best practices, new technologies, and emerging trends in software verification and QA.

Make better product quality by improving test coverage.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer, you will work as part of a Research and Development team, and will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Verification Engineer - Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design Verification team, responsible for validating the most advanced networking silicon in the world. Our team ensures functional correctness, quality, and reliability across the entire design flow. We combine state-of-the-art methodologies with a collaborative, startup-like culture, while being backed by the stability and resources.
Your Impact
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success of Silicon One, powering the next generation of Internet infrastructure.

As a Formal Verification Engineer, you'll play a crucial role in ensuring the quality and reliability of our Graviton product line. You'll own the complete verification lifecycle, from planning through execution, collaborating with cross-functional teams to deliver quality results in a fast-paced environment.

Key job responsibilities:
Drive formal verification efforts for complex hardware designs.
Develop comprehensive verification plans and execute them independently.
Collaborate with design, system and verification teams.
Identify and resolve design issues using formal methods.
Contribute to methodology improvements and best practices.

We are now looking for a Chip Design Verification Engineer. We are seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company.

What you'll be doing:

Develop shared verification code and solutions to be widely used by the chip design team.

Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.

Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.

Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.

Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

Collaborate with designers, verification specialists to accomplish your tasks.

Develop training sessions.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.