Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

0-5 years of experience in Physical Design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

2+ years of experience in physical design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 5 years of experience

Should be a power user of synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) with 5+ years of experience.

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modeling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Great teammate, ownership, self-learning skills, and ability to work autonomously.

Ways to stand out from the crowd:

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience.

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus).

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

Proficiency using Python, Perl, Tcl, Make scripting.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Ownership, self-learning skills, and ability to work autonomously.

Ways to stand out from the crowd:
Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality).
Knowledge in Tcl/Perl/Python.
Versatile.
Great teammate.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Communication Engineering/Computer Engineering.

3+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design). Less experienced engineers with high university grades will also be considered.

High Level of English.

Ways to stand out from the crowd:

Background in Specman.

Knowledge in Verilog.

Requirements:
What we need to see:

B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering or equivalent experience.

3+ years of experience in Verification.

High Level of English.

Ways to stand out from the crowd:

Knowledge of PCI Express standard.

Validated experience in Verification or RTL Frontend ASIC Design (Chip Design).

Background in Specman.

Background in RTL uArch & coding.

Requirements:
What we need to see:

B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering or equivalent experience.

5+ years of overall hands-on experience.

Validated experience in Verification or RTL Front-end ASIC Design.

High Level of English.

Ability to work as part of a team.

Ways to stand out from the crowd:

Background in Specman or UVM.

Knowledge in HDL (Verilog/VHDL).

Requirements:
What we need to see:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
Experience in RTL verification.
Self-motivated, ability to work independently and drive tasks to completion
A great teammate with good communication and interpersonal skills.

Ways to stand out from the crowd:
Knowledge in Specman, Verilog.
Knowledge in Networking.