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We are looking for best-in-class Students for a Verification role in our Chip Design team to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Verification of unit block level, include planning and executing of a verification plan.

Work with the state of the art tools and methodologies.

Exposed to real life complexities of Chip Design infrastructure challenges.

We are looking for a Test Development Engineer to join our team. This role will work as part of a team driven by the development of our networking and interconnect products. Do you have a passion for automation development, test program development, code writing and looking for sophisticated and significant topics? We will be happy to have your skills on the team. You will handle various projects across teams, build test plans, automate test specification and execution. You will continuously innovate and develop scalable, reliable, high-performance systems and tools to enable the next generation of Interconnect products.

What Youll Be Doing:

Will work on projects across multiple functional teams from different geographies throughout the product lifecycle.

Develop test plans, execute testing via automation and/or manually for all supported hardware releases.

Work with cross-functional teams across engineering, thermal, mechanical and HW to identify test requirements.

Develop automation and tools for our hardware releases and test environment.

Debug of HW & SW failures in interconnect product, Isolate the problem and get to the root cause.

Design and build technical processes to address business issues.

Deploy the test solution to the production sites and provide support if needed.

Train personnel on the required processes and operations of complex test systems.

We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Act as Partition/Unit level physical design technical leader and focal point.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies, and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be part of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

We are now looking for a Chip Design Student for the NVIDIA SOC team.

As a Chip Design Student at NVIDIA, you'll join a group of passionate engineers and students to design and implement the next generation state of the art DPU SOC chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency.

What you'll be doing:

Work in a combined design and verification team which develops some of the SOC silicon core units

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.

Partner closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Leading and mentoring Physical Design-Backend team.

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for a talented Senior HPC and AI Networking Performance Research and Analysis Engineer to join our Performance group.

The ideal candidate will profile and analyze AI workloads on large GPUs and CPUs scale clusters for distributed Deep Learning LLM training focusing at the collectives communication and networking.

You will work and interact with many types of HW and platforms such as HCAs, Switches, CPUs, GPUs, and Systems.

You will experience with and develop performance analysis tools and methodologies to dive deeply into the details, understand performance expectation, limitations, and bottlenecks.

What you'll be doing:

Experience and research AI workloads and DL models specifically tailored for large-scale deep learning LLM training on our supercomputers with a focus on High-performance networking.

Benchmarking, Profiling, and Analyzing the performance to find bottlenecks and identify areas of improvement and optimizations, with a strong emphasis on networking aspects.

Implement performance analysis tools.

Collaborating with many teams from HW to SW to provide performance analysis insights.

Define performance test planning , set performance expectations for new technologies and solutions, and work to reach the performance targets limits.

We are looking for an experienced, highly motivated software engineer to join our Chip Design Technologies team. As a member of this team, you will be exposed to the world of EDA software development. This field merges electrical and software engineering to create software tools and solutions used to expedite the design and validation of the next generation of product designs. In our company, these products are aimed at advanced data centers, and power AI revolution across the world.

What you'll be doing:

Leading the charge in developing software tools and solutions, crucial for creating cutting-edge design validation methodologies for us.

Enhancing and refining our suite of in-house tools, used in design validation flow.

Collaborating with designers, verification specialists to ensure your solutions seamlessly integrate into our design validation process.

In this hybrid role based in LOCATION, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

looking for backend Developer to build web applications with JS frameworks and backend technology. R&D Solutions leads the market by adopting innovative technologies & providing top-notch development solutions, and now we are looking for you - a JAVA Developer to join our growing team. If you are excited about developing complex marine systems, love working with worldwide clients, and want to be part of a highly experienced & motivated team using best practice methodologies - you belong with us!
* The perfect candidate will be a highly communicative individual with excellent development skills and passion to learn and build awesome web apps that are used by millions.
* You will design, plan, develop, and manage JAVA -based software applications.
* You will collaborate with experienced software engineers in the team.

We are looking for a Backend Tech Lead.
2+ years of experience working as a tech-lead
Lead an outstanding development team focused on extraordinary intelligence systems deployed both on-premises and in cloud-native environments.
Our Micro-Services approach, coupled with a one-of-a-kind architecture, supports hundreds of customers daily in their real-time communication needs.
Collaborate with cutting-edge and varied technologies, including Python, Java, Docker, Micro-Services, AWS and Android environment, while meeting a high development standard.
Impact & Responsibilities:
Design, build and maintain the architecture for unique end-to-end mobile and backend solutions
Responsible for training and mentoring developers
Collaborate closely with fellow development teams and product management.
Explore emerging technologies to enhance stability scalability and performance.
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