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We are looking for an excellent Senior Firmware Verification Engineer to join the Firmware team. The company Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed
What you will be doing:
Work closely with the architecture and different software and hardware design teams.
Implement new features for our company NIC and Switch firmware.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.
Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.

We are now looking for a AI Networking Chip Security Architect we are looking for an outstanding security architect with Networking focus to design, validate, and guide implementation of secure architecture of its core products. The candidate is expected to: define problems & deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the Security organization. Leaders in this role will help reduce risk, threats, and vulnerabilities and design new security technologies in our company networking products.
What youll be doing:
Own the security requirements for next gen networking chips in a verity of product lines.
Lead new security technologies definitions into the roadmap of our company Networking devices.
Work with technical and senior leadership staff to turn business directives into functional implementations.
Collaborate between multiple business units and development groups to ensure robust, secure service posture from design to implementation.
Provide hands-on security engineering expertise across a wide variety of platforms.
This role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:
Chip Security Architecture
Embedded System Architecture and Design
Security around interconnects and protocols
Security Standards
Cryptography.

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.