דרושים » הנדסה » System Engineer

We are seeking an experienced HW Team Leader to drive the engineering efforts behind our electronic systems. This role will focus on enhancing the testability, production efficiency, and quality of our products by defining Design for Testability (DFT) strategies, developing production test solutions, and leading failures investigation and correction.
What You'll Do:
Lead and mentor a team of highly skilled hardware engineers.
Drive execution in a fast-paced, multi-project environment.
Own and evolve our Design for Testability (DFT) strategy and guidelines.
Lead end-to-end development of production test solutions and test facilities.
Drive root-cause investigations, failure analysis, and product improvement initiatives.
Collaborate closely with R&D, manufacturing, and quality teams to ensure product reliability and production readiness.

Required Senior DFT Lead
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required Design Verification Vision Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, youll work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in our edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.

Required Physical Design Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
You will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis is expected. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible.
Responsibilities
Lead the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Establish and direct the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge and latch-up (ESD/LU), and biased highly accelerated stress test (b/HAST)) and conduct in-depth failure analysis to resolve quality issues.
Analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (e.g., early life failure (ELF), time-dependent dielectric breakdown (TDDB), or negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.

Required Senior SOC DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

Required Senior Silicon DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

Required Design Team Manager, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required Design Verification IP Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive the distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in our edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.

Required Chip Test Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.