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as a cpu design Verification engineer, you will work as part of a research and development team building verification components, constrained-random testing, system testing, and verification closure.
as part of our server chip design team, you will verify complex digital designs. you will collaborate with design and Verification engineers in active projects and perform verification. you will be responsible for the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.behind everything our users see online is the architecture built by the technical infrastructure team to keep it running. from developing and maintaining our data centers to building the next generation of google platforms, we make product portfolio possible. we're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. we keep our networks up and running, ensuring our users have the best and fastest experience possible.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for stimulus and corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
apply close coverage measures to identify verification holes and to show progress towards tape-out.

we are looking for an experienced SW engineer with desire and ability to contribute and lead cutting edge network management system of most powerful super-computers in the world. our team is growing, and we are looking for hardworking and self-motivated engineers to lead building of advanced, high scale sdn management solutions. you will be part of a dynamic team, working with amazing people. this crucial role will give you a rare opportunity to craft and deliver a new class of data center nms product line.
what you'll be doing:
the team develops infrastructure for monitoring and gathering telemetry from production environments, running on the worlds largest supercomputers and datacenters.
the work environment is dynamic and challenging; we are innovating and inventing software products at the forefront of technology in terms of performance, scalability, and features.
our team works closely with other engineering teams to co-design new features and software apis

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join tel-aviv/beer-sheva group, working on verification in the field of encryption accelerators.
verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve verification and might involve any or all aspects of chip development including micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office.

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

seeking a highly skilled and experienced PCIe Validation Engineer to join our Silicon and System Validation team, playing a key role in the companys core products. This position involves building a complex validation environment from scratch for pre and post silicon, defining test plan execution and debugging failures while collaborating with cross-functional teams. In this role, you will take ownership of the validation from Emulation thru bring-up to product release in quality that meets Next silicons standards.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch and gpu technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th ai revolution. our team delivers world class chips solutions for hpc, ai infrastructures, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of nvidia's core technology.
you will take part in the ai revolution led by nvidia, working on cutting edge architecture.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity