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לפני 19 שעות
חברה חסויה
Location: Yokne`am and Tel Aviv-Yafo
Job Type: Full Time
our company has transformed computer graphics, PC gaming, and accelerated computing for over 25 years. Its a unique legacy of innovation fueled by great technology-and amazing people.
Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU and Networking products act as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. Looking into the future, power management and power optimizations present a huge challenge in the development of silicon throughout all the development life cycles. Together, we can meet the challenge. Join the team and see how you can make a lasting impact on the world. The networking architecture team seeks a highly-skilled, leading engineer to explore, define and assimilate power optimization methods across all design disciplines.
What you'll be doing:
You'll be responsible for developing architectures, algorithms, models, and methodologies aimed to improve the power consumption of our DPU and NIC products.
Play a key role in facing these challenges and lead the research of innovative power techniques and power modeling that will drive our solutions to the next level.
Take an active part in HW design reviews.
Requirements:
Bachelor or Master (advantage) degree in science fields from a known institute
At least 3 years of experience or equivalent in computer architecture such as performance analysis, power management, power optimization and characterization, power modelling, etc.
Strong EE fundamentals, knowledgeable in digital design, frontend, and backend practices, power analysis, and characterization.
High-level programming (SystemC or C++) and scripting (Python) skills is considered an advantage.
Exceptional analysis skills. Excellent problem-solving, teamwork, and interpersonal skills.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (e.g., Lint, CDC, etc.).
Experience with SOC architecture.
Experience in logic design.
Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced Extensible Interface (AXI), or Advanced RISC Machines (ARM) processors family.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats motivated by great technologyand outstanding people. We are leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world!
We are now looking for a CPU Architect in the CPU team! our company needs a passionate engineer who is comfortable in both the hardware and software worlds to help us push the boundaries of CPU and SoC simulation. Todays complex CPU designs rely on detailed functional models to aid in verification, and to support the running of complex workloads for architectural exploration. Such workloads often span CPU and GPU, such as gaming, Deep Learning (DL), autonomous vehicles, and High-Performance Computing (HPC). These models and workloads enable important decisions to be made about future company CPU architectures and allow us to gain confidence in our HW implementations.
What you'll be doing:
Develop cycle-accurate architectural performance and power models for the CPU core of a complex high performance system-on-a-chip.
Use models to analyze architectural tradeoffs related to CPU Performance and Power, identifying performance bottlenecks on deep learning (DL) workloads, high-performance computing (HPC) workloads, as well as industry standard benchmarks like SPECInt and SPECFp.
Propose micro-architectural alternatives that fit within area, timing and power constraints for the design.
Work with the performance verification team to validate the model, and to root cause disconnects between model projections and design (RTL).
Requirements:
BS/MS in EE, CE, or CS
4+ years of experience with a focus on CPU microarchitecture, or equivalent experience
Excellent C/C++ programming and debugging skills
Understanding of computer architecture
Ways to stand out from the crowd:
Knowledge in CPU memory & caching microarchitecture
Knowledge in OOO microarchitecture for hyperscale CPUs
A history of generating innovative microarchitectural ideas to improve performance, from an idea to a working feature on silicon
Knowledge of the ARM ISA & microarchitecture
Understanding of SoC and GPU architecture.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SOC Performance Technical Lead, you will drive the success of our System-on-Chip (SoC) products. You will be focused on ensuring our SoCs deliver maximum performance, power efficiency, and cost-effectiveness. You will be a multi-disciplinary expert who can bridge the gap between deep learning, advanced algorithms, and hardware/software design to create innovative solutions for current and future product lines.
You will lead and oversee a team, setting the technical direction and making critical decisions on frameworks, methodologies, and tools. You will require a collaborative approach with various teams to ensure alignment with organizational goals.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
Exercise open source benchmarks, analyze the results, and find optimization opportunities.
Develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
Analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre and post-silicon environments.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering, or equivalent practical experience.
8 years of experience in SoC or CPU performance and power modeling, analysis, and debugging.
Experience in programming languages such as C, C++, Python, or Similar.
Experience in computer architecture, including in areas like interconnects, traffic QoS, distributed caches, and I/O flows.
Preferred qualifications:
Experience with hardware description languages like Verilog or SystemVerilog.
Experience in pre and post-silicon analysis and debugging.
Experience in productizing features that enhance the performance or power characteristics of a design.
Experience in building fast, accurate SoC/CPU performance models in C++.
Experience in one or more functional areas, such as coherent fabrics (e.g., AMBA CHI/AXI), memory controllers (e.g., LPDDR5, DDR5), or I/O controllers (e.g., PCIe, CXL).
Ability to independently identify, troubleshoot, and solve complex performance problems.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Participate in test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).
Experience with SoC or IP architecture.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.
Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8412913
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דיווח על תוכן לא הולם או מפלה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with verification techniques, and the full verification life-cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8413236
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our companyusers worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8413505
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
our company has been defining computer graphics, PC gaming, and accelerated computing for more than 25 years. With an outstanding legacy of innovation, driven by phenomenal technology, and extraordinary people, we are looking for a strong technical senior architect to join us in shaping the future. Senior Architects are innovators who can translate business needs into workable technology solutions. Their expertise is deep and broad. They are hands on, producing both detailed technical work and high-level architectural designs.
As a Senior architect in the Advanced Development team, you will explore technological challenges on accelerate networking and building AI data centers. Research new transport functions and semantics for optimizing AI workloads. You will also be leading architectural and development efforts across numerous technological fields, related to the modern data center, such as distributed AI and deep learning solutions, data analytics, High Performance Computing (HPC), Software Defined Networking (SDN), virtualization, storage, and more.
What youll be doing:
Enhance our company's GPU Networking offerings for accelerating AI workloads, such as our company Dynamo or our company NIXL.
Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.
Lead architecture and design of such technologies.
Lead proof-of-concept development to evaluate and drive such technologies.
Requirements:
Hold a M.Sc. or Ph.D. in Computer Science, Electrical or Computer Engineering from a leading university (or equivalent experience).
12+ years of industry experience (or equivalent) in systems architecture or related fields.
Experienced in virtualization, networking and storage.
Experienced in either Windows or Linux drivers, with a very good background of the other OS.
Deep understanding of performance profiling and optimization techniques, together with defining and using HW offloads.
A teammate with a can-do attitude, high energy and excellent interpersonal skills.
Ability and flexibility to work and communicate effectively in a multi-national, multi-time-zone corporate environment.
Ways to stand out from the crowd:
Shown research track record.
Have experience and passion for system architecture, CPU/GPU/memory/storage/networking.
Stellar communication skills.
Knowledge in Deep Learning frameworks and AI communication libraries (NCCL, UCX, MPI and equivalents).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8465872
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דיווח על תוכן לא הולם או מפלה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
1 ימים
Location: More than one
Job Type: Full Time
our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing.
we are looking for a passionate, modern software engineer or junior architect early in their career. The role involves developing and prototyping new scalable training and inference advancements using our companys Spectrum-X AI fabric.
This role offers a rare opportunity to work on innovative AI and networking technologies, building prototypes that influence the development of large-scale AI systems. You will help improve AI applicationnetwork interaction by refining communication, crafting congestion control, contributing to NIC and switch capabilities, and enhancing AI factory performance at scale.
What youll be doing:
Prototype end-to-end solutions to improve distributed training and disaggregated inference performance.
Analyze and optimize communication flows across application, transport, and network layers.
Develop system software spanning communication libraries, drivers, and firmware integrations.
Collaborate with hardware, firmware, and SDK teams to co-design network features.
Validate and integrate prototypes into our companys AI infrastructure and products.
Requirements:
Bachelor's or Master's Degree in Computer Science or Electrical Engineering
0-2 years of experience in relevant fields.
Programming knowledge in C/C++
Ability to work closely with architects and R&D teams.
Passion to learn and innovate independently.
Ways to stand out from the crowd:
Demonstrated innovation and leadership turning prototypes into impactful product features.
Understanding of Networking Protocols Ethernet, InfiniBand is an advantage.
Ability to quickly adapt to new technology and go deep into new areas.
Contributions to open-source projects, academic papers, or performance benchmarking tools.
Background in AI factory architectures, distributed inference, or network telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8465419
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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Location: More than one
Job Type: Full Time
We are seeking a highly motivated SoC Architect to join our team and define the next generation of our companys high-performance networking SoCs. Our Ethernet and NVL switch silicon powers the world's most advanced AI compute clusters - from hyperscale GPU systems used to train and inference massive foundation models, to the AI factories shaping the future of computing.
As an SoC Architect at our company, you will drive end-to-end SoC definition, connecting system-level requirements with chip-level implementation across multiple domains. You will work closely with cross-functional teams to craft scalable, power-efficient, and feature-rich SoCs that enable the next leap in networking and AI infrastructure.
What You'll Be Doing:
Lead SoC architecture across multiple teams and disciplines - including firmware, security, debug, power management, and peripheral/IP owners - ensuring holistic architectural alignment and system coherence.
Ensure next-generation architectures meet the requirements and constraints of all stakeholder teams, and drive clear specification and communication of those requirements.
Architect and analyze multi-chip solutions, including die-to-die connectivity, chip partitioning, package/board constraints, system requirements, chip fabric, PCIe subsystem and how SoC subsystems must support them.
Define top-level SoC structure: subsystem partitioning, interconnect, memory subsystem, coherency, clocking, power architecture, and system integration.
Define system flows: power up sequences, boot sequences, software update.
Own the SoC architecture specification and guide it throughout the entire product lifecycle - concept, modeling, implementation, and silicon bring-up.
Perform trade-off analyses across performance, area, power, and feature complexity to drive architectural decisions.
Collaborate deeply with chip architects, logic design, verification, physical design, firmware, and system software to ensure seamless integration of all SoC components.
Contribute to innovation and long-term architectural direction, including patent development.
Requirements:
BSc or MSc in Electrical Engineering, Computer Engineering, or related field
6+ years of experience in SoC or chip architecture, microarchitecture, or complex ASIC design
Strong understanding of SoC fundamentals - interconnects, memory systems, coherency, clock/power architecture, security, and HW/SW integration
Ability to work across hardware, firmware, and system software boundaries with strong system-level reasoning
Hands-on experience writing and owning architecture specifications
Proven ability to collaborate across many teams and drive alignment in complex technical environments
Ways to Stand Out from the Crowd:
Expertise in networking, switch silicon, high-speed IO, or data-path acceleration
Experience defining multi-chip or disaggregated architectures (e.g., chiplets, advanced packaging, die-to-die protocols)
Experience with fabric and memory subsystem.
Strong background in system modeling, performance analysis, or traffic simulation
Experience with security architecture, power management, or debug infrastructure.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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