דרושים » הנדסה » DFT Engineer

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

we are looking for a Senior Silicon DFT Lead, Google Cloud
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

we relentlessly strive to create products that enrich peoples lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out..
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.

we are looking for a Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

we are looking for a Senior Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

We are looking for a Product & Test ATE Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will be responsible for performance analysis for an end-to-end networking stack using your infornation of RDMA based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

Were looking for a talented and driven Integration Team Lead to join our System Engineering group. In this role, youll lead the integration team, working closely with system engineers, V&V, and other R&D functions to bring cutting-edge technologies into reality.
Responsibilities:
Lead and manage the integration team, including task planning, setting priorities and mentoring team members
Be the technical focal point for integration-related activities
Oversee system testing and manage the handover process from Integration to V&V
Lead system bring up activities
Responsible for troubleshooting efforts and resolving problems in a timely manner
Maintain a broad understanding of the entire system and stay up to date with the latest version
Lead by example, motivate, empower and develop team members to reach their full potential
Establish strong working relationships with System Engineering and V&V teams to ensure high-quality delivery
Collaborate closely with multiple cross-functional teams across the organization

We are seeking a Digital Electrical Design Engineer with extensive experience in board-level digital design, high-speed interfaces, and embedded systems. In this role, youll be a technical lighthouse within our Hardware R&D teamguiding complex, high-speed digital designs from concept through production. Youll collaborate closely with firmware engineers, system architects, and other cross-functional teams spread across multiple global sites. While prior quantum or cryogenic experience isnt required, an interest in learning about these cutting-edge fields is a plus.
Key Responsibilities:
Digital Board-Level Design: Architect, design, and implement advanced digital solutions involving FPGAs, microcontrollers, and high-speed communication interfaces (multi-GHz range).
High-Speed Signal Integrity: Develop and validate clocking solutions up to the tens of GHz range and handle GT lines to ensure robust, reliable performance.
End-to-End Development: Own the entire hardware lifecyclefrom concept and schematic design in Altium to layout review, testing, and production release.
Design for Manufacturing & Test (DFM/DFT): Integrate manufacturing and testing considerations into your designs, collaborating with supply chain and production teams to ensure scalability and cost-effectiveness.
Technical Collaboration: Work closely with firmware engineers, system architects, and cross-site R&D teams to ensure seamless hardwarefirmware integration.
Remote Coordination: Engage in significant remote collaboration with minimal travel, leveraging Agile and Kanban methodologies for project execution.
Subject Matter Expert: Serve as a go-to resource for digital design best practices, helping to maintain high engineering standards across the organization.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for a networking stack using the knowledge of Remote Direct Memory Access (RDMA) based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.