דרושים » הנדסה » Senior Logic Design Engineer

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04/08/2025
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a highly experienced Logic Design Engineer who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding experienced DevOps Engineer customer base.
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation).
Requirements:
BSc in electrical/computer engineering or relevant military background- Must
At least 7 years of experience- Must
Proven track record in RTL coding with System Verilog- Must
Experience with System Verilog- Must
VCS, Vivado - Advantage.
This position is open to all candidates.
 
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04/08/2025
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
Required Senior uArch Design Engineer
Tel Aviv Israel
A global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Engineering, or related field- Must
8+ years of experience in RTL design using Verilog/SystemVerilog- Must
Proven experience in designing micro-architecture for complex systems
Strong system-level understanding and problem-solving skills.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Senior SOC RTL Design Engineer, Google Cloud
Responsibilities
Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience.
8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).
Experience with PCIe (PCI).

Preferred qualifications:
Experience in scripting languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of System-on-a-Chip (SoC) architecture.
Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).

Preferred qualifications:
Experience with design sign off and quality tools (e.g., Lint, Cyber Defense Center (CDC), etc.).
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Junior Design Engineer, Google Cloud, Network
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and field-programmable gate array/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience architecting networking ASICs from specification to production or equivalent practical experience.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Experience in the following areas: performance debugging and optimization of complex workloads, design of performance tools, compiler design and code optimization, high-performance software development techniques, concurrent programming, or multi-core computer architectures.
Experience architecting networking switches, end points, and hardware offloads.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We're seeking a passionate and experienced Senior System Engineer to play a pivotal role in shaping the technical vision and driving the next generation of intelligent maritime solutions. If you're excited about working in a fast-paced, multidisciplinary environment and leveraging cutting-edge technologies, we want to hear from you!
What You'll Do:
As a Senior System Engineer , you'll be the technical lead for system-related aspects of our products. You'll work closely with cross-functional teams to design, implement, and deliver robust solutions that redefine maritime operations. Your responsibilities will include:
Define System Architecture: Establish hardware and software requirements for new and existing products.
Collaborate Cross-Functionally: Work alongside Product Management and R&D Team Leaders to ensure seamless design, implementation, and testing.
Understand Customer Needs: Analyze market trends and customer feedback to shape technical solutions.
Lead System Integration: Oversee hardware and software integration, ensuring smooth interactions between components.
Support Field Operations: Provide technical support for field trials, customer deployments, and production processes.
Problem-Solving: Identify, communicate, and resolve technical challenges throughout the development lifecycle.
Mentorship: Guide and mentor technical team members, fostering a culture of innovation and continuous learning.
Requirements:
Experience: 5+ years as a System Engineer working on multidisciplinary products, from concept to delivery.
Education: B.Sc. in Electrical Engineering, Computer Engineering, or Optics Electronics.
Technical Skills: Hands-on experience with hardware/software integration and system design.
Sensors Expertise: Proven experience working with sensors and related technologies.
Design Knowledge: Strong understanding of hardware, mechanical design, and integration processes.
External Collaboration: Experience working with third-party equipment providers and contractors.
Documentation: Skilled in writing comprehensive system requirements and specifications.
Communication: Fluent in English with excellent verbal and written skills.
Bonus Points:
Background in cameras, including thermal imaging systems.
Experience with networking and video streaming technologies.
Knowledge of the maritime technology sector.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Senior SOC and IP Design Engineer, Google Cloud
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).

Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Senior SoC and IP Design Engineer, Google Cloud

Responsibilities
Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience in logic design.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (e.g., Lint, CDC, etc.).
Experience with SOC architecture.

Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Knowledge of assertion-based formal verification.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
Excellent problem solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Junior SoC IP Design Engineer, Google Cloud
Responsibilities
Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with design sign off and quality tools (Lint , CDC , etc.).

Preferred qualifications:
Master's or PhD in Computer Science or related technical fields.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of SOC architecture.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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6 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a talented software engineer. You will take part in developing our core product infrastructure. The challenge is to design and develop complex security components that can be integrated in a generic and flexible way for Android & IOS 3rd party applications. The code is developed with C / C ++, Python, JAVA, and Objective- C. Responsibilities
* Creatively developing, designing, and delivering new infrastructures and security features.
* Improving, testing, and debugging our current infrastructure according to customers' needs.
* Continuously learn and evaluate new technologies in the everlasting effort to perfect our product.
Requirements:
* B.Sc. in Computer Science / Electrical Engineering / Computer Engineering.
* At least 3 years of development experience in a development team of complex enterprise systems.
* At least 2 years of experience in C / C ++ programming.
* Experience in multi-threading principles and programming.
* Experience in Python, JAVA, Linux, and Git.
* Great team player who knows when and how to push independently when needed.
* Strong communication skills.
Advantages:
* Experience in native mobile application development in Android or IOS.
* Experience Objective- C programming.
* Experience in NDK and JNI for Android.
* Experience with SDK development or integration. Advantages.
* Experience in reverse engineering for Android.
* Knowledge in Cyber security and Networking.
About the company:
Our mission is to protect every mobile app in the world and its users. We provide mobile brands with the only patented, centralized, data -driven Mobile Cyber Defense Automation platform. Our platform delivers rapid no-code, no-SDK mobile app security, anti-fraud, anti-malware, anti-cheat, anti-bot implementations, configuration as code ease, Threat-Events threat-aware UI / UX control, ThreatScope Mobile XDR, and Certified Secure DevSecOps Certification in one integrated system. With us, mobile Developers, cyber and fraud teams can accelerate delivery, guarantee compliance, and leverage automation to build, TEST, release, and monitor the full range of cyber, anti-fraud, and other defenses needed in mobile apps from within mobile DevOps and CI/CD pipelines. Leading financial, healthcare, m-commerce, consumer, and B2B brands use us to upgrade mobile DevSecOps and protect Android & IOS apps, mobile customers, and businesses globally. Today, our customers use our platform to secure over 50,000+ mobile apps, with protection for over 1 billion mobile end users projected.
We are an Equal Opportunity Employer. We are committed to diversity, equity, and inclusion in our workplace. We do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other characteristic protected by law. All qualified applicants will receive consideration for employment without regard to any of these characteristics.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we are looking for a Hardware Emulation Engineer, Google Cloud
Responsibilities
Help to maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in infrastructure.
Support emulation team members in debugging hardware, tooling, and project specific issues.
Help bring up external interfaces (e.g., USB, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms, and create test cases for tool issues encountered in the emulation compile and runtime flows.
Requirements:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience with emulation systems including maintenance, upgrades, methodology enhancements and Electronic Design Automation (EDA) tools (e.g., Palladium or Zebu).
Experience with coding in Perl, TCL or Python.

Preferred qualifications:
Master's degree in Electrical Engineering.
Experience in deploying EDA tools into distributed environments.
Experience with system administration, networking, and security systems.
Experience with Register-Transfer Level (RTL) design, Verilog, simulation (e.g., VCS, Incisive, Questa), System Verilog (e.g., DPI and transactors), and assertions.
This position is open to all candidates.
 
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