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Location: Tel Aviv-Yafo
Job Type: Full Time
Required Senior Software Engineer, Cloud Filestore
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
Filestore provides a fully managed Network File System (NFS) service for Enterprise Cloud users who need file storage to replace their on-premise hardware when they move to the Cloud.
This is an amazing opportunity to join and impact an early-stage, hi-growth project that builds from the grounds-up a new infrastructure for Cloud Filestore - a shared, distributed, enterprise-level filesystem.
Responsibilities
Define, design and implement key components, built from the ground-up, for the next-gen of Filestore focusing on performance, reliability, efficiency and resilience.
Help grow and mentor the team, be a part of a well-experienced group and impact the critical architecture and design decisions.
Work with peers from other aspects of the product development lifecycle, including all filesystem engineering teams, product management, program management, SRE, UX/UI.
Work with product and customers, to best fit future requirements.
Develop software primarily in C++.
Requirements:
Minimum qualifications:
Bachelors degree or equivalent practical experience.
5 years of experience with software development in one or more programming languages.
3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture.
Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
5 years of experience with data structures and algorithms.
1 year of experience in a technical leadership role.
Experience in computing, distributed systems, storage, or networking.
Experience with software development in C++ or C.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847289
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling.
Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.
Preferred qualifications:
Proficiency with scripting languages commonly used in hardware automation (e.g., Tcl, Python, or Perl).
Deep familiarity with ASIC physical design flows and methodologies, including synthesis, place and route (P&R), formal verification, and clock domain crossing (CDC).
Solid fundamental knowledge of semiconductor device physics and transistor characteristics.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847274
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דיווח על תוכן לא הולם או מפלה
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
07/10/2026
Location: Shamir
Job Type: Full Time
we are looking for a AI / Computer Vision Algorithm Engineer.
Key Responsibilities:
AI/Computer Vision Engineer to develop image-processing algorithms for next-generation ophthalmic diagnostic devices.
Full time, Hybrid
Develop advanced computer-vision algorithms for medical imaging.
Detect biomarkers related to specific use cases
Build models supporting diagnostic decisions.
Train deep-learning models (CNNs, ViT, Autoencoders).
Work with Python, PyTorch/TensorFlow, OpenCV.
Requirements:
B.Sc./M.Sc. in CS or a related field.
3-6 years of experience in CV/ML/DL.
Strong Python and AI library experience.
Medical imaging experience - an advantage.
Ability to collaborate with ophthalmologists and clinical teams.
Experience integrating models into medical devices and real‑time imaging systems.
Strong problem‑solving and research orientation.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847270
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Physical Design Lead, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
articipate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in silicon implementation and chip integration.
Experience in ASIC development teams.
Experience in managing physical design teams working on digital designs that produce and deliver silicon.
Preferred qualifications:
Experience in extraction of design parameters and analyzing data trends.
Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
Understanding of circuit design, device physics, and deep sub-micron technology.
Knowledge of delivery of high complexity silicon in technology process nodes.
Ability to lead cross-functional teams.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847267
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סגור
דיווח על תוכן לא הולם או מפלה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in RTL design cycle from IP to SoC, from specification to production.
8 years of experience in execution teams management.
Experience in the following areas: RTL design, design quality checks, physical design aspects of RTL coding, and power.
Preferred qualifications:
Experience with synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with a scripting language like Python or Perl.
Experience with design for test and its impact on design and physical design.
Knowledge of one of the following areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, ARM processors family.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847258
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how the subsystem interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847237
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847232
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff ChipDev Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will have the opportunity to find the perfect blend of software design practices and hardware development complexity. You will be a hardware engineer with software proficiency.
Responsibilities
Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with application-specific integrated circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Create software solutions that improve the hardware design process through automation.
Propose, design and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.
12 years of experience in software development using various programming languages, algorithms, and data structures.
5 years of experience creating developer tools (such as automated systems or compilers) to enhance code health, quality, and velocity.
3 years of experience in a technical leadership role.
Preferred qualifications:
Experience with ASIC design, debug, and verification flows.
Experience evaluating multiple vendor solutions and driving tool decisions/design improvements.
Experience with design verification techniques, including constrained-random simulation, formal property verification, or static verification.
Experience working with register-transfer level (RTL) teams and design integration methodologies that improve team productivity and velocity.
Experience with software architectural elements across domains, including CAD, physical design, architecture, digital design, silicon validation, and design verification.
Ability to resolve complex, ambiguous problems that do not have established precedents.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847227
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Rehovot and Tel Aviv-Yafo
Job Type: Full Time
Required SoC Test and Product Engineer Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and outsourced semiconductor assembly and tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices.
You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement strategies for high-volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, defective parts per million reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and return merchandise authorization managing.
Drive product leadership for silicon engineering organization from architectural definition to global availability.
Collaborate with cross-functional teams across the globe including ATE and SLT test engineering, quality and reliability, packaging, supplier management and operations to build, deploy, and maintain a high volume manufacturing screening solution.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in product engineering or test engineering.
3 years of experience in people management, developing employees.
Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).
Preferred qualifications:
Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement.
Experience with product engineering, supply chain data analytics and diagnostics for high volume manufacturing and NPI.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, statistical analysis (e.g., JMP), yield management systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
Understanding of skew lot definition, data collection, characterization, data analysis and report.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847208
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
07/10/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We're looking for a driven, energetic, and curious BDR who loves connecting with people, opening doors, and creating new business opportunities. This is a hands-on role at the heart of our go-to-market team, where you'll identify and engage potential customers, spark meaningful conversations, and help build sales pipeline.
You'll work closely with our Sales team to understand our target market, reach the right people, and turn prospects into qualified opportunities. We're looking for someone with excellent communication skills, a strong sense of ownership, and a proactive, results-driven mindset - someone who isn't afraid to pick up the phone, thinks creatively about how to get a prospect's attention, and stays motivated even when hearing "no."
If you're ambitious, persistent, and excited by the challenge of creating something from scratch, we'd love to meet you.
Key Responsibilities:
Prospecting Expertise: Strategically identify and enrich prospect lists against our Ideal Customer Profile (ICP) to build a consistent pipeline of qualified leads.
Dynamic Multi-Channel Outreach: Run structured, sequence-driven outreach across phone, email, and LinkedIn. Spark interest, translate technical capability into business value, and move prospects from cold to curious.
Rigorous Qualification: Apply our Rules of Engagement vertical-specific ICP signals, discovery questions, and disqualification criteria, to make sure only real, sales-ready opportunities get handed off.
Collaborative Partnership: Partner closely with Account Executives on meetings you've scheduled, delivering clean handovers and staying engaged through the early sales funnel to help convert your pipeline into revenue.
Market & Competitive Awareness: Stay sharp on where wins, including displacement opportunities against competing data providers and bring that intel back into how you prospect and position.
Skill Enhancement: Participate in ongoing coaching and training, sharpening your outbound technique and vertical fluency as expands into new markets and use cases.
Requirements:
Minimum of 1 year of cold-calling, lead generation, account management, or sales experience, preferably at a B2B startup or equivalent solution-selling skills
Hardworking, committed, and driven to grow and succeed
Self-motivated and comfortable in a fast-paced, dynamic environment
English as a mother tongue, and preferably one additional language (Spanish, German, French, Italian, or others)
Experience using HubSpot CRM or a similar contact management system
A sales hunter, go getter approach
Proven ability to translate technical product functionality into clear client value
Aptitude for technology
Excellent time management and organizational skills
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847201
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Software Engineer, EDACloud
About the job
Our Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
The EDACloud team was established to provide tools and support for our rapidly expanding hardware engineering teams. We develop and manage unique software for deploying industry-standard Electronic Design Automation (EDA) tools on Cloud. As a Software Engineer, you will be focused on developing automation, including backend Remote Procedure Call (RPC) services, for seamless tool deployment. Additionally, we're developing cloud-based solutions to scale these workflows effectively, and generate unique insights for our users using advanced machine learning techniques. This critical environment directly impacts hardware creation.
Responsibilities
Design and deploy AI-driven strategies to streamline routine operations and power strategic programs.
Design, implement, and support the transition of custom chip design environments onto standardized, cloud-hosted virtual developer workstations.
Design and implement highly available, distributed services from the ground up, moving beyond automation scripts to robust, production-grade microservices.
Help define the technical roadmap for the teams service stack, evaluating new technologies and cloud-native tools to improve future scalability and performance.
Identify and refactor technical debt within the codebase to improve modularity, maintainability, and code quality.
Requirements:
Minimum qualifications:
Bachelor's degree in a technical field or equivalent practical experience.
5 years of experience with data structures and algorithms, and software development in one or more programming languages.
3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture.
Preferred qualifications:
3 years of experience in Cloud Systems Design.
Experience interacting directly with end users/product aptitude.
Ability to apply Artificial Intelligence/Machine Learning techniques to generate insights for users.
Excellent communication, presentation, and problem solving skills.
Passion for technology and delivering exceptional user experiences.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847199
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing, etc. You will develop/define design options for performance, power and area.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience in logic design and debug with Design Verification (DV).
Experience with microarchitecture and specifications.
Preferred qualifications:
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (e.g., Lint, CDC, VCLP, etc.).
Experience in a scripting language like Python or Perl.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847193
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
07/10/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are seeking a DevOps Engineer, at the mid or senior level, to join our infrastructure team, reporting directly to our DevOps Team Leader. Depending on experience, this role will either contribute to or help drive advanced infrastructure initiatives - from system design through production hardening - as we raise the bar for operational excellence across the company.
The immediate challenge: Vetric operates a high-volume, multi-account AWS environment. You will help solve complex delivery, scaling, and operational problems along the way. Scope and ownership will be calibrated to your experience level.
Responsibilities:
Contribute to Cloud & Migration Strategy: Work alongside our DevOps Team Leader to help plan and execute our migration from ECS Fargate to Kubernetes (EKS) without downtime, while maintaining our existing cloud estate.
Advance Infrastructure as Code: Design and implement modern, modular IaC frameworks utilizing Terraform and OpenTofu to ensure consistent, multi-environment deployments.
Improve Enterprise CI/CD: Evolve our delivery pipelines (GitHub Actions, OIDC federation) at scale, reducing developer friction and elevating deployment safety across dozens of services.
Support Data-Intensive Infrastructure: Help maintain the performance, capacity, and resilience of our high-volume data layer (ClickHouse, ScyllaDB, DynamoDB, RDS, Redis) and event-driven messaging pipelines.
Strengthen Reliability & Observability: Help maintain organization-wide reliability standards using open, modern telemetry stacks (OpenTelemetry, Coralogix, Grafana), ensuring on-call operations are driven by signal, not noise.
Balance Growth & Governance: Participate in technical tradeoff decisions that balance velocity, least-privilege security, zero-trust access (Tailscale), and FinOps cost efficiency.
Requirements:
3+ years of hands-on DevOps, Infrastructure, or Cloud Engineering experience, with real production exposure in high-throughput, data-intensive environments.
Cloud Expertise: Solid working knowledge of AWS architectures, including compute, networking (VPC, DNS, segmentation), IAM, and scalability patterns.
Kubernetes Experience: Hands-on experience running and/or optimizing Kubernetes clusters (EKS) in production.
IaC & Automation Proficiency: Strong experience with Terraform and solid scripting/software engineering skills in Python, Go, or TypeScript, plus confident Bash.
Container & Pipeline Ownership: Familiarity with container workloads (ECS/Docker) and modern CI/CD systems (GitHub Actions) using safe rollout strategies.
Observability: Experience designing and/or operating observability and alerting stacks (metrics, logs, traces, SLOs).
Collaborative Communication: Pragmatic, clear communicator who thrives in a high-velocity, autonomous team environment and builds trust through sound technical judgment.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847192
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like: remote direct memory access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in transmission control protocol (TCP), IP, ethernet, peripheral component interconnect express (PCIE) and dynamic random access memory (DRAM) including network on chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
Proficiency in procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847176
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
07/10/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a R&D Director.
As an R&D Director at Vetric, youll lead multiple engineering teams and their leaders, owning the technical direction, execution, and organizational development of a critical area within our R&D organization.
Youll be responsible for translating company priorities into an effective engineering strategy, building strong teams and leaders, and ensuring we deliver scalable, reliable systems at high velocity.
Youll work closely with R&D leadership and cross-functional stakeholders to shape priorities, drive execution across teams, and continuously improve our engineering organization, architecture, and production excellence.
Responsibilities:
Lead and scale engineering teams and leaders, developing strong Team Leads and engineers while building a culture of ownership, accountability, collaboration, and continuous growth.
Own the engineering strategy and technical direction for your domain, translating business and product priorities into clear technical priorities, architecture decisions, and execution plans.
Drive execution across multiple teams, ensuring effective prioritization, alignment, and delivery of complex initiatives while managing dependencies and removing organizational and technical blockers.
Own production excellence and system reliability, driving high standards around scalability, performance, observability, incident management, and continuous improvement of our production environment.
Drive engineering excellence across the group, establishing and continuously improving standards and practices around architecture, development processes, code quality, and operational readiness.
Own organizational and capacity planning for the group, including team structure, hiring, resource allocation, and developing future technical and managerial leaders.
Partner with stakeholders across the company, including Product, Customer Success, and company leadership, to ensure engineering priorities are aligned with customer needs and broader business objectives.
Drive measurable impact, using data and engineering metrics to evaluate priorities, improve execution, and ensure resources are focused on the areas that create the greatest impact.
Requirements:
8+ years of software engineering experience, with significant experience building backend and large-scale production systems.
4+ years of engineering leadership experience, including experience leading multiple teams and managing or mentoring engineering leaders.
Strong technical background in modern backend architecture, distributed systems, and high-scale, high-performance environments.
Experience developing backend services with TypeScript and Node.js.
Strong hands-on understanding of cloud infrastructure, preferably AWS, as well as CI/CD and modern production environments.
Proven experience driving complex technical initiatives across multiple teams from strategy and architecture through execution and production.
Strong ability to balance technical excellence, delivery speed, business priorities, and long-term scalability.
Impact-driven mindset, with the ability to use data to prioritize effectively, measure outcomes, and maximize the impact of engineering resources.
Excellent leadership and communication skills, with the ability to influence technical and business stakeholders and create alignment across teams.
Creative and solution-oriented, with a strong sense of ownership and a can-do attitude. Comfortable operating in a fast-paced environment, making decisions under uncertainty, and adapting quickly to changing business needs.
Passion for data and for building reliable, high-scale infrastructure.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847164
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