לוח משרות דרושים הייטק תוכנה משרה מלאה

help build an always-on, low-overhead gpu profiling service that runs in production, scales across cluster environments, and delivers actionable insights for ml workloads. you will be hands-on delivering our profiling solutions across system software, drivers, and cuda to make profiling continuously available and reliable.
what youll be doing:
develop low-overhead, high-reliability implementations in C / C ++, with bounded cpu/memory budgets.
lead end-to-end feature delivery spanning user-mode components, driver/platform layers, and performance counter/trace providers.
establish profiling models that integrate with existing ml/ai workflows (e.g., pytorch/xla) to turn low-level signals into actionable insights.

our company networking system validation group is growing, and we are hiring a junior switch system Validation engineer. as a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. you'll gain networking and switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like quality-of-service, performance, logic correctness, and ai features. 
you will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages. 
you should have a good grasp of software development in different fields, such as Python scripting, Embedded software, and device firmware. it's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans. 

what you will be doing: 
work in a combined design and verification team specializing in switch full chip works
understand the switch architecture and build on  TEST plan accordingly 
develop full chip  TEST collaterals/suites, maintain regressions, debug failures and sign-off coverages 
maintain TEST suites to facility emulation and/or silicon platforms checkout as well

seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

we seek a highly motivated and experienced  system architect specializing in data -center, ai fabric, and ethernet networking to join our team of experts and help shape the future of high-performance ml/ai computing. you will have the opportunity to work on some of the most pioneering technologies and help drive the innovation of our next-generation networks. you will play a key role in defining end-to-end solutions, networking protocols and features, interworking with orchestration systems, and help address new business opportunities in exciting areas. our architects also represent nvidia in open-source projects, technical conferences, and standard development organizations.
what you'll be doing:
explore new technologies and end-to-end solutions for our ethernet networking platforms.
be familiar with data -center and ai fabric network topologies, ai/ml clusters operation and network usage, as well as with the ethernet switch platforms' design and characteristics.
define robust architectures and technical requirements for network operating systems and end-to-end solution offering for ai/ml workloads' needs and highly performing network operations.
lead the work with r&d and validation teams, providing technical guidelines and close support and thorough reviews for detailed designs and TEST plans.
collaboration with architects across various fields, including chip design, firmware, hardware platforms, and system teams.
close work with Product Marketing, program managers, and account managers to ensure the successful execution of projects.
support engagements with key customers, issue patents, publish white papers and blogs, and be proactive in technical forums and industry working groups.
promote innovation through the design and implementation of proof-of-concept (poc).

seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using nvidias spectrum-x ai fabric. this role offers a rare chance to pioneer ai and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale ai systems. improve ai app-networking connection by refining communication, crafting congestion control, coding nic firmware, and expanding switch sdk features for enhanced ai factory efficiency. your work impacts large ai system development, scaling, and speed.
what youll be doing:
prototype end-to-end solutions to improve distributed training and disaggregated inference performance.
analyze and optimize communication flows across application, transport, and network layers.
develop system software spanning communication libraries, drivers, and firmware integrations.
collaborate with hardware, firmware, and sdk teams to co-design network features.
validate and integrate prototypes into nvidias ai infrastructure and products.

we are seeking an excellent Software manager to join to nvos  sw group in yokneam ilit. you will have the opportunity to lead a development team responsible for the software of the next-generation networking products while being hands-on with development activities. we drive the data growth of the worlds biggest companies. with dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. are you ready for the challenge?
what you'll be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the nvos .
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
support internal and external customers for any nvos related items.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the sw/fw relationship.
innovate! bring our networking products to shine in the customers view

we are looking for a 100% hands-on Storage services software engineer to join the block Storage group. you will be a member of a team that builds the next generation block Storage capabilities. you will work closely with a variety of teams and architects including the networking team, and external customers. you will take part in defining the software architecture and implementation of the most advanced Storage services! services that will need to meet extreme performance and scalability demands! we have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.
at our company, we work, think and learn as a team. we thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. the rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.
what youll be doing:
100% hands-on coding role in C language, Kernel and userspace
research, design, implement and TEST, new and existing, distributed Storage services and features of our block Storage solution, in both host and dpu environments.
acquire understanding of the algorithms, the technicalities and the interaction with other components across our block Storage ecosystem.
analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox Kernel modules and often in other components. drive new solutions based on any issues that arise

our company is leading groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu -- our invention -- serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables groundbreaking creativity and discovery, and powers inventions that were once considered science fiction, including artificial intelligence to autonomous cars. come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we're seeking a Senior Software Architect to help co-design next-gen data center platforms and scalable communications software.
DL and hpc applications have a huge compute demands and already run at scales of up to tens of thousands of gpus. gpus are connected with high-speed interconnects (e.g. nvlink, pcie) within a node and with high-speed networking (e.g. infiniband, ethernet) across nodes. efficient and fast communication between gpus directly impacts end-to-end application performance. this impact continues to grow with the increasing scale of next generation systems. this is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. are you ready to build the new and innovative technologies that will help realize our vision?
what you will be doing:
investigate opportunities to improve communication performance by identifying bottlenecks in today's systems.
design and implement new communication technologies to accelerate ai and hpc workloads.
explore innovative solutions in hw and sw for our next generation platforms as part of co-design efforts involving gpu, networking, and sw architects.
build proofs-of-concept, conduct experiments, and perform quantitive modeling to evaluate and drive new innovations.
use simulation to explore performance of large gpu clusters (think scales of 100s of 1000s of gpus)

conduct in-depth performance characterization and analysis on large multi-gpu and multi-node clusters.
study the interaction of our libraries with all hw (gpu, cpu, networking) and sw components in the stack
evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available
triage and root-cause performance issues reported by our customers
collect a lot of performance data ; build tools and infrastructure to visualize and analyze the information
collaborate with a very dynamic team across multiple time zones

our company is leading the way in groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.
come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we are looking for a motivated partner enablement engineer to guide our key partners and customers with nccl. most DL /hpc applications run on large clusters with high-speed networking (infiniband, roce, ethernet). this is an outstanding opportunity to get an end to end understanding of the ai networking stack. are you ready for to contribute to the development of innovative technologies and help realize our vision?
what you will be doing:
engage with our partners and customers to root cause functional and performance issues reported with nccl
conduct performance characterization and analysis of nccl and DL applications on groundbreaking gpu clusters
develop tools and automation to isolate issues on new systems and platforms, including cloud platforms (azure, aws, gcp, etc.)
guide our customers and support teams on hpc knowledge and standard methodologies for running applications on multi-node clusters
document and conduct trainings/webinars for nccl
engage with internal teams in different time zones on networking, gpus, Storage, infrastructure and support.

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are now looking for a power optimization and analysis engineer! our company prides ourselves on having energy-efficient products. we believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. as part of the u/arch team in the switch group, you will be responsible for analyzing full chip and unit-level power data and driving the fe/be asic teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. key responsibilities include developing techniques to model, analyze, and reduce power consumption of our switches product line.
as a member of switch u/arch team, you will collaborate with architects, performance engineers, software engineers, asic design engineers, and physical design teams to study and implement power analysis and reduction techniques for our next generation switches. your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
what you'll be doing:
use internally developed tools and industry standard pre-silicon gate-level and rtl power analysis tools, to help improve product power efficiency.
develop and share best practices for performing pre-silicon power analysis.
perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
interact with architects and rtl designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
select and run a wide variety of workloads for power analysis.
prototype new architectural features in verilog and power analysis.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.