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Required Senior Memory Subsystem Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Architect representative
Job Description
The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.

Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Required Senior Core Power Management Architect
Job Description
Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers.
The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invens corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Were looking for a highly organized, detail-oriented Open Innovation Coordinator to join our Technology Planning team. This entry-level role is ideal for candidates with strong analytical skills, clear communication, and a background in software-hardware co-design or computer architecture research. Youll support the Technology Planning Manager and team by analyzing technical trends and helping identify new technologies and collaboration opportunities to advance our innovation strategy.
Key Responsibilities:
Conduct deep-tech research, reviews and analyse on emerging technologies using academic, market, and industry sources.
Track developments in areas such as AI infrastructure, AI Data Movement and other related areas.
Synthesize findings into clear, concise internal summaries and presentations.
Support project coordination: timelines, deliverables, and cross-team communication.
Prepare for and participate in international meetings, including collaboration with China-based and European teams.
Manage logistical and administrative tasks for innovation team.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation.
The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Our Research and Innovation Center, is looking for an experienced hands-on software architect with expertise in Cloud, AI, and Distributed Systems to join our AI-accelerated Cloud Storage group. The team designs and develops cutting-edge cloud technologies that power next-generation AI applications, optimizing performance, scalability, and efficiency.
The role involves both high-level system understanding and low-level grasp of the connection between storage and AI, to push the boundaries of cloud infrastructure for AI workloads. If you want to be part of something bigger, if you are a team player with excellent communication skills and the motivation to revolutionize AI-driven cloud technologies, youre welcome on board!

DRS RADA is a global leader in cutting-edge radar solutions for active military protection, counter-drone systems, critical infrastructure security, and border surveillance. Our mission is to deliver reliable, innovative technologies that safeguard lives and assets. Role Summary: As the Quality Program Manager, you will spearhead the quality assurance strategy across R&D, Product, and Operations, ensuring our systems meet the highest standards of reliability, compliance, and performance. You will lead Quality team, define scalable processes, and drive a culture of continuous improvement in a fast-paced, Agile environment. Key Responsibilities: Strategic Quality Leadership
* Develop and execute the Quality Plan, aligning with program milestones and business objectives.
* Establish KPIs, metrics, and risk-based QA methodologies to monitor product reliability and process adherence.
* Lead internal/external audits and ensure compliance with defense industry regulations. Cross-Functional Collaboration
* Partner with R&D, Product, and Delivery teams to embed QA early in the development lifecycle (SDLC).
* Drive Agile/Scrum QA practices, including CI/CD pipelines, automated testing, and failure analysis.
* Mentor QA teams and engineers, fostering technical growth and accountability. Process Excellence & Innovation
* Design and optimize QA processes for hardware/software integration (e.g., radar systems, embedded software).
* Leverage statistical analysis(e.g., Weibull, MTBF) to predict and improve system reliability.
* Implement corrective/preventive actions (CAPA) based on field data and test results.

CodeValue is looking for a highly motivated Full Stack Engineer to join our core engineering team and help us shape and build innovative products end-to-end. As part of a lean and agile R&D environment, you'll have real ownership — from design and architecture to implementation and deployment. You'll work across the stack: building scalable microservices and crafting modern, high-performance frontends. If you're passionate about delivering clean, scalable solutions that create real business impact — we want to meet you.

At our company, we help enterprises and service providers empower their data -driven competitive advantage at scale. We are a leading provider of enterprise-class Storage solutions. The companys software-focused architecture delivers sub-millisecond latency, full availability, and scalability with a significantly lower total cost of ownership than competing Storage technologies. We are seeking a skilled Senior system Testing Engineer to join our company. You will collaborate with cross-functional teams to identify and report bugs, verify bug fixes, and develop testing strategies. You will be responsible for ensuring that the system TEST team delivers high-quality results, meets deadlines, and maintains effective communication with stakeholders.
Responsibilities:

* Develop and implement system testing strategies and processes.
* Collaborate with cross-functional teams to identify and report bugs.
* Verify bug fixes and ensure they meet the required quality standards.
* Develop and maintain TEST cases, plans, and documentation.
* Ensure timely delivery of high-quality TEST results.
* Stay up-to-date with industry trends and best practices in manual testing.