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The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

In this role, you will be driving CPU architecture exploration by analyzing performance metrics (latency, power, code density) across benchmarks and CPU families. Investigate optimization opportunities through customizing ISAs and microarchitecture features to improve power and performance. You will develop simulation analysis tools and toolchain infrastructure for CPU/SOC architectures. You will collaborate closely with Apple's algorithm and software teams to build efficient CPUs, enhancing performance for diverse use cases.
Description
You will be responsible to create analysis tools to assist in architecture exploration. You will define and simulate CPU features and develop supporting tool chains including simulators, analysis tools, compiler, etc.. You will collaborate with SW and algorithm teams as well as implementation teams to define and build efficient CPUs that integrate seamlessly into various subsystems.
Responsibilities
Work with SW and algorithm teams for optimization and customization of ISAs, CPU architecture, and micro architecture features
Create and analyze benchmarks for CPU and SOC subsystem architectures
Develop architectural and performance simulators
Define and develop toolchain infrastructure

A successful, fast-growing, startup located in Raanana. We are looking for an experienced system engineer to participate and lead the development of a radio-based drone detection and mitigation system as part of the company products.
Responsibilities:
Lead features and platforms from ideas to releases.
Guide and participate in the research and analysis of both proprietary and standard radio communication protocols.
Define requirements and guide multi-disciplinary teams (SW, Algorithms, DSP, and FPGA) through implementation and debugging.
Analyze and define complex system behaviors, state machines, algorithms, and event-response logic, including radio link budget considerations.
Perform independent, hands-on debugging and optimization for system problem-solving using tools like MATLAB, Python, Excel, and other log analysis software.
Create and maintain comprehensive system-level documentation.
Gain a deep understanding of the full system to guide and support testing and validation teams, helping define methodologies, tools, and coverage strategies.

The role includes development of Automated TEST Equipment (ATE) TEST stations, including digital tests and RF tests. The engineer will be responsible for TEST system development from the requirements definition stage through delivery of the TEST system to the customer and its maintenance. The role also includes technical characterization and definition of project documents such as SPEC, SOW, TRD. Education Required: Bachelors degree in Electrical Engineering.

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.

You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are seeking a talented Technical Program manager to join our software group. In this high-visibility, hands-on role, you will drive forward the development of our software platform by defining the product and technical direction.

Responsibilities:
Collaborate with other team leaders to establish the product and technical vision for the software group.
Lead the planning, development and implementation process of cross-functional teams focused on delivering cutting-edge technology and products.
Oversee project monitoring, reporting, and risk management, from initiation to delivery, addressing intergroup dependencies to ensure timely and successful completion.
Lead process and methodology improvements, proactively addressing issues to achieve business goals.
Help define our next-generation product roadmap and New Product Introduction (NPI) process.

We are looking for a talented Code Generation and Optimization Expert. We are looking for a self- , independent engineer to join the team that builds the software infrastructure for accelerating the system in large scale compute environments like data centers and HPC using new CPU core technology. Working on the cutting edge and future ready systems. We work in a development culture that is diverse, flexible and challenging. For persons looking to make an impact and influence the future of computing with personal growth options.

The CodeGen team is developing core components in the automated optimization process that adapts our unique hardware architecture to run any HPC & AI applications, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.

We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge CodeGen team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building NextSilicons next-generation runtime compiler.

Responsibilities:
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how ASIC subsystem interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design & Power Methodology Team Manager within the Server Chip Design team, you will be responsible of managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.