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Required ASIC Design Engineering Technical Leader
Meet the Team
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for a Staff QA Architect to join our elite team, contributing to the development of one of our strategic products for Cloud Security.
In your role, you will be responsible for developing and maintaining high-quality work procedures, leading the team to achieve better quality.
You will be involved in the full feature lifecycle - from gathering requirements with the product team to release - ensuring quality at every stage, including bug management and observability and defining QA work procedures, guidelines, and designing the entire testing process.
The ideal candidate will be responsible for leading quality activities across solution-level features, ensuring the highest standards of quality are met. This role requires a proactive individual with excellent leadership and communication skills, capable of driving quality initiatives and fostering a quality-focused mindset within the organization.
Comprehensive understanding of the product's functionality, target use cases, and the value it delivers to customers.
Lead the quality efforts across multiple interfaces with a proactive and assertive approach, serving as the key point of contact for all quality-related matters.
Define, implement, and manage QA processes, promoting a quality-driven culture and managing the quality backlog.
Define the overall testing strategy and tooling stack across integration, regression, and load/performance testing.
Drive an automation-first approach - collaborating with developers to ensure code is testable and observable.
Lead root-cause analysis for escaped bugs and define improvement actions.
Own CI quality metrics and dashboards (e.g., build stability, test flakiness, regression coverage).
Influence decisions regarding test environments, mocks, test data, and production parity.
Collaborate with the centralized quality group to ensure E2E test coverage.
Quality Point of Contact: Serve as the primary point of contact for quality-related matters concerning the unit or the cross-group feature.

As a Principal Engineer SQA, you will be collaborating with a SaaS development team that use the latest technologies in continuous delivery to secure the top enterprises in the world. You will gain a deep understanding of the product's functionality, target use cases, and the value it provides to customers.
Your Impact
Serve as the senior QA professional in the R&D team.
Commit to the quality of all released content.
Take an active role in process inspection and continuous improvement.
Actively track team tasks, analyze testing needs, and define QA activities and ownership.
Plan, define, and execute tests as part of team QA related activities.
Analyze and challenge existing testing coverage, both manual and automated.
Create test plans to determine the steps needed to increase confidence in product quality.
Monitor the test and production environments, using DevOps tools.
Assimilate appropriate QA activities within every step of the SDLC.
Define, implement, and manage QA processes, including test plans and procedures.
Actively participate in feature testing during development to ensure adherence to specifications and quality standards.
Efficiently analyze logs and reproduce customer issues for quick resolution.
Maintain and prioritize open issues and bugs to ensure effective tracking and resolution.
Design and execute automated tests, manage test environments, and develop tools to improve testing efficiency and coverage.

Required PHY Post Silicon Validation Engineer
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Silicon One group as part of the silicon development
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Who You'll Work With:
You'll be part of our Group driving our game changing next generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.
Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

We are seeking a Volunteering, Inclusion & Diversity Operations Student to join our Team and support the execution of volunteering, Inclusion & Diversity, and employee community initiatives across us.

In this role, you will help bring projects to life by supporting logistics, coordination, administration, and on-site execution, working closely with internal teams, employees, external vendors, and community partners.

Location: Herzliya (primary); travel to Haifa as needed.

Availability: Minimum 4 days per week.

Responsibilities:
Support planning and execution of volunteering projects, I&D initiatives, and employee community programs.
Manage logistics: scheduling, supplier coordination, materials procurement, registration, and event preparation.
Coordinate with internal stakeholders, external vendors, nonprofits, and community partners.
Provide on-site/external venues support during events and activities.
Handle multiple parallel projects with precision and attention to detail.
Help identify ways to improve processes, create efficiencies, and support scalable project execution.

As part of your role, you will design, implement, and deploy products and infrastructures that will directly increase our stability and quality while reducing our time to market. You will have end-to-end ownership from individual development environments and SCM/Build/CI servers to our production system on AWS.
Your Impact:
Design and manage Continuous Integration/Deployment Services, including build, packaging, and deployment.
Design, document, implement, and maintain scripts to enhance current and future build and release processes.
Incorporate new development projects into existing build structures.
Continually evaluate tools and technologies to improve the overall release process.

we are looking for a Senior Product Owner to join our CORA (Generative) AI group. We build AI agents, frameworks and shared infrastructure that power GenAI capabilities across the company, enabling our companys product lines to adopt agentic workflows safely, reliably, and at scale.
As the groups Senior Product Owner, you will bridge the gap between emerging AI technologies and production-grade reality. You will own the roadmap for embedding agentic AI solutions across the company, balancing product impact with long-term architectural excellence. Collaborating closely with Product Managers and Engineering, you will define how agent-based intelligence can best serve our diverse product lines, while driving the development of both shared infrastructure and bespoke agentic solutions throughout the entire lifecycle - from ideation and implementation to deployment and evaluation. Your goal is to gradually build a platform that empowers every company product to adopt AI safely, reliably, and at scale.
Enable the Ecosystem:Treat other company product teams as your customers. Deeply understand their product landscapes to ensure our AI platform is flexible enough to support their unique functional needs while maintaining its robustness and architectural integrity.
Architect the Agentic Roadmap:Translate high-level product and engineering vision (the Why & How) into a concrete plan (the What & When) - forming a prioritized backlog of actionable epics, user stories, and functional specifications that guide the R&D team towards building the platform.
Strategic Liaison:Serve as the primary authority for stakeholders outside the development group, providing deep clarity on platform capabilities, framework logic, and how architectural changes will impact the broader product ecosystem.
Tactical Orchestration:Partner daily with R&D to steer the development process - supporting sprint planning, refinement, and high-quality delivery, resolving functional ambiguities, adapting the plan to real-time technical/product insights, and ensuring the team maintains high velocity while staying aligned with the strategic vision.
Champion Iterative Value:Foster continuous feedback loops between stakeholders and technical teams to enable rapid iteration and deliver meaningful value.

Required PHY System
Job Description
Join the PHY system team at a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are looking for a Senior Security Researcher to join our specialized Red Team. In this role, you will focus on the complex boundary where hardware meets software. You will hunt for vulnerabilities in the microarchitecture, memory management, and execution pipelines of modern CPUs and GPUs, as well as in the low-level code which runs on it. If you enjoy bridging the gap between hardware primitives and kernel-level exploits, and have a passion for uncovering side-channels or architectural logic flaws, this is the team for you.

Responsibilities:
Architectural Red Teaming: Design and execute targeted adversarial campaigns against the hardware/software interface of modern SoCs, specifically focusing on CPU and GPU.
Vulnerability Discovery: Conduct deep-dive vulnerability research into microarchitectural behaviors, side-channels, and hardware-assisted security features.
Exploit Development: Develop proof-of-concept exploit chains that bridge hardware vulnerabilities into kernel space, demonstrating real-world impact.
GPU & Compute Security: Analyze GPU driver interfaces, command processors, and execution units, particularly in the context of modern compute workloads and hardware acceleration.
Mitigation Bypass & Analysis: Evaluate and attempt to bypass modern hardware mitigations (e.g., Pointer Authentication, Memory Tagging, virtualization boundaries).
Cross-Functional Collaboration: Partner with hardware engineering and software kernel teams to translate your red team findings into robust, architectural-level mitigations.