Searching for an experienced ASIC chip design engineer to take part in building the chip SoC, including integration of complex design clusters and analog IPs.
The design team develops design integration automation and tools, which enables effective chip level connectivity.
Requirements:
BsC in Electrical Engineering.
Excellent interpersonal and communication skills.
Independent experienced design engineer.
Knowledge of ASIC flow and BE/verification constraints.
Experience in Verilog RTL design, chip clock scheme, reset scheme.
TCL, Perl scripting.