לוח משרות דרושים מהנדס VLSI, לחיפוש זה נמצאו 5 משרות !

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.Hybrid model).

Join our elite team, where we transform modern technology and bring groundbreaking innovations to life. As a Senior Hardware Engineer, you'll be part of a visionary group driving the future of AI, robotics, and autonomous driving. Our Israel-based team thrives on solving complex challenges while promoting a collaborative and inclusive environment where bold ideas flourish. This is your chance to contribute to a legacy of excellence and make an indelible impact on the world!

What you'll be doing:

Crafting, developing, and implementing advanced hardware solutions that power next-generation AI and computing platforms.

Collaborating with cross-functional teams to ensure seamless integration of hardware components.

Conducting rigorous testing and validation to deliver flawless performance in our products.

Analyzing and optimizing system performance to meet strict quality standards.

Partnering with software engineers to determine hardware requirements and ensure successful implementation.

Leading and mentoring junior engineers, encouraging a culture of innovation and collaboration.

We are rebuilding the way chips get built, and were looking for a senior engineer to help lead that transformation.

This is a full-stack platform role on the team responsible for the development environment behind our silicon. You will help define how agentic orchestration and durable execution become first-class parts of the chip-design workflow.

Were looking for someone who has built complex systems before - across backend, frontend, and infrastructure - and is ready to set the technical direction for what comes next.

What You'll be doing:

Architect and lead full-stack EDA platforms end to end, from data models and backend services to the frontends engineers use every day - while making key technical and build-vs-buy decisions.

Own the infrastructure these platforms run on at scale, including CI/CD, containerization, observability, on-prem compute, and cloud-native Kubernetes environments.

Set engineering standards across the team by leading design reviews, improving reliability and developer experience, and mentoring engineers.

Act as a technical leader across silicon, backend, and design-automation teams, helping turn fragile manual flows into dependable automated systems used by many engineers.

Scd is Hiring Mixed-Signal Test & Validation Engineer (IR ROIC) Job Description: We are looking for a hands-on Test & Validation (post silicon) Engineer to join our VLSI design group, focusing on Infrared Readout Integrated Circuits (IR ROICs).
This role sits at the intersection of circuit design, silicon validation, and system-level characterization. You will work closely with analog and mixed-signal designers to ensure testability is built into the design from early stages, and later take ownership of silicon bring-up, validation, and electro-optical characterization.
Responsibilities: • Define and drive DfT for analog/mixed-signal: observability, controllability, test modes, and measurement access • Contribute in design/layout reviews to ensure testability; define validation strategy pre–tape-out • Lead first silicon bring-up; execute block and full-chip validation; debug with design teams • Plan and run characterization across PVT and modes; analyze noise, linearity, DR; correlate sim ? silicon • Collaborate with Physics/System teams on electro-optical and radiometric performance of the hybridized ROIC • Build and maintain lab setups; develop automation (Python) for data acquisition and analysis; document methods/results • Perform failure analysis and debug issues to identify root causes and implement corrective actions. • Document test results, methodologies, and procedures for future reference. • Stay updated with the latest advancements in VLSI testing technologies and methodologies.