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We are looking for a Hardware Failure Analysis Engineer to join the Interconnect FA team. This role will be part of the Product Engineering organization supporting our advanced high-speed interconnect and optical communication products.

The ideal candidate will lead failure investigations of complex hardware systems, including electro-optic modules, high-speed electrical interfaces, and optical interconnect components, supporting both production and customer-returned units. The role requires strong analytical skills, hands-on laboratory debugging, and the ability to drive root cause investigations across electrical, optical, and system domains.

What you'll be doing:

Lead failure analysis investigations on interconnect products including optical modules, AOCs, and high-speed hardware platforms.

Review architectural design aspects (electrical, optical, mechanical, process, and firmware) to identify potential design or integration issues.

Design, develop, and execute debug and validation test plans to identify root cause of hardware failures in production or customer-returned units.

Perform hands-on electrical and optical debugging using laboratory equipment and automated test systems.

Correlate electrical, optical, and system-level measurements to identify failure signatures.

Work closely with internal engineering teams (design, validation, manufacturing, reliability) and external partners to drive root cause and corrective actions.

Document investigation results and deliver clear technical FA reports summarizing findings and recommendations.

Help shape how AI data centers are powered. At our company, we're a global leader in smart energy technology, with over 3,000 employees, offices in more than 20 countries, and millions of installations worldwide. we are expanding its innovation into the fast-growing world of AI data -center power infrastructure. Building on our leadership in solar, Storage, and power electronics, we are creating a next-generation Power Ecosystem - integrating Solid-State Transformers (SST), Battery Energy Storage Systems (BESS as UPS), and advanced power-conversion platforms designed for the AI era. Join our UPS data Centers group and play a key role in developing our company's next generation of high-performance power conversion and backup power solutions for data centers. As a Senior Hardware Design Engineer, you will take ownership of hardware development throughout the entire product lifecycle-from concept and design through validation and mass production-working on complex, multidisciplinary systems in a fast-paced environment. What will you be doing?
* Design and develop advanced power electronics hardware for UPS systems.
* Lead hardware development from concept through mass production, including schematic design, board development, validation, and product release.
* Design analog and power electronic circuits for high-power applications.
* Perform hardware bring-up, debugging, validation, and optimization.
* Plan and execute electrical, thermal, EMI/EMC, and reliability tests to ensure product performance and compliance.
* Collaborate closely with Mechanical, Software, system Engineering, Integration, and Manufacturing teams throughout the development lifecycle.
* Support design reviews, root cause analysis, and continuous product improvements.
* Work with laboratory equipment to evaluate, troubleshoot, and validate hardware designs.
* Contribute to system architecture discussions and technical decision-making.

Country:
Israel
City:
Modiin

The System product engineer is responsible for stabilizing hardware products from the first build unit through ramp-up and transition to high-volume mass production. This role plays a critical part in ensuring product quality, yield, and test robustness for our cutting-edge platforms by leading debug infrastructure development, systematic failure analysis, and data-driven continuous improvement across the NPI lifecycle.

What you'll be doing:

Own end-to-end product stabilization from first article to production release.

Develop and maintain hardware debug infrastructures, tools, and methodologies to support efficient root cause analysis.

Monitor, analyze, and improve yield performance during NPI.

Perform deep-dive failure analysis and root cause investigations to improve product robustness, quality, and throughput.

Improve test stability, coverage, and repeatability while reducing false failures.

Collaborate closely with Mechanical NPI engineers, Test Development teams, R&D, and manufacturing partners.

Apply data analysis techniques to identify systemic issues, trends, and optimization opportunities.

Join our multidisciplinary integration team and take part in the development and validation of advanced RF-based systems. The role involves hands-on work with complex hardware and software systems, prototype setup and testing, troubleshooting, and close collaboration with multiple R&D teams.

Responsibilities include:
Integration and testing of complex multi-module systems.
Involvement throughout the full development lifecycle of RF and digital systems.
Setup and validation of prototype systems at both hardware and software levels.
Identifying hardware/software issues and driving technical solutions.
Working closely with software, hardware, and final testing teams.
Participating in challenging, development-oriented projects with strong growth opportunities.

Imagine what you could do here. , new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.


What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

Required CPU Design Integration Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools.
Involve in project development and convergence with the highest quality, agreement with issues as they arise through design and implementation, or equivalent relevant experience.
Connect between RTL design, physical design, DFT, external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.
Ensure chip quality by implementing best practices and implementing quality control measures.

Were looking for an experienced SW Engineer to join our Architectural Team, where you'll design and develop our hardware simulators that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics. You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behavior.
Responsibilities:
Develop new hardware simulators and continue evolving existing ones.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.

What you will be doing:
Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for hardware architecture, system embedded software, user interface and high-level design.
Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.
Define the architecture of implementing physical layer standards into our ASIC devices.
Involved in standard bodies activities and definition of next generation protocols.
Define features for the phy layer, to exploit interoperability between different generations of communication.
Be involved in product definition and the high-speed protocols that the networking devices will support.
Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.
Become focal point for our physical layer networking communication devices.

We are looking for an Embedded Software Engineer for performance verification and profiling.
You will join the Virtual Platforms and Performance Verification team in the EyeQ Platform Group (EPG), working on current and next-generation ADAS/AV systems.
Virtual platforms, performance models, and profiling tools are core components of the EPG infrastructure. These tools are used during the pre-silicon phase for hardware architecture optimization and software development, and in the post-silicon phase for software performance optimization.
What will your job look like:
Performance verification of EyeQ SoC designs
Development of hardware virtual platforms
Running hardware benchmarks and correlating virtual platform results with silicon measurements
Development of tracing and profiling tools for CPU performance analysis and optimization
Close collaboration with hardware architects and software, OS, and algorithm teams.

As a chip design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

Join the Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced FPGA Design Engineer who will play a pivotal role in developing , designing and optimizing FPGA solutions for our cutting-edge projects. Your expertise will drive innovation and excellence in digital design as part of the detection team in CT\AMI.

Your role :
Develop FPGA logic using VHDL / Verilog.
Design and implement high-speed data paths and interfaces such as DDR, PCIe, Ethernet.
Perform simulation, verification, timing closure, and debugging.
Integrate FPGA with soft processors (such as MicroBlaze / Nios), sensors, ADCs/DACs, and other system components.
Support system bring-up, lab validation, and debugging at both board and system level.
Collaborate closely with hardware, firmware, software, and system teams.
Support and participate in architecture discussions and design reviews.
Read and understand board schematics to support integration and troubleshooting.
Perform lab and system-level testing after component changes or design updates.
Document FPGA design, interfaces, and implementation details.

we are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.

Responsibilities
Develop and build complex emulation models for coming generations of accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system