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Required ATE Design Engineer (IL)
Hod Hasharon
The ATE Engineer is responsible for working with engineering teams to develop the ATE testing stations. We are seeking a highly experienced ATE Hardware and SW Engineer with a strong background in RF, digital, and system-level testing. This role requires deep hands-on knowledge and the ability to design, develop, and support advanced test equipment for complex electronic systems used in production environments.
What will you do:
Design and develop Automated Test Equipment (ATE) for RF, digital, and mixed-signal products at board and system levels.
Collaborate with R&D and manufacturing teams to define and implement test strategies and solutions.
Analyze and understand system schematics, block diagrams, and interface requirements to create robust and reliable ATE.
Support production lines by troubleshooting test failures and optimizing test processes for yield and throughput improvements
Interface with software and firmware teams to integrate hardware with control and automation systems.
Evaluate and select test instruments, fixtures, and measurement techniques based on product specifications.
Maintain documentation for test systems, including design files, calibration procedures, and troubleshooting guides.
Train technicians and engineers in ATE operations and maintenance.

Required Senior Board Designer
Role Summary:
Serve as a key contributor within a hardware design team developing advanced ultrasound systems.
Lead and execute high‑quality PCB design with a focus on performance, reliability, manufacturability, and cost.
Collaborate with internal engineering groups and external partners to develop complex system modules.
Provide ongoing support, maintenance, and continuous improvement for legacy hardware platforms.
Job Responsibilities:
Drive the design and development of digital and analog circuitry across the full product lifecycle - from concept and prototyping through mass production.
Perform circuit analysis, simulations, and signal integrity verification for both analog and high‑speed digital designs.
Apply critical thinking and problem‑solving skills to identify issues, propose solutions, and communicate findings clearly.
Utilize Cadence/OrCAD tools for schematic capture and PCB layout.
Work effectively with cross‑functional teams, including mechanical, firmware, manufacturing, and external ODM partners.
Lead electrical design activities with external teams, ensuring technical alignment and high‑quality delivery of system sub‑modules.
Produce clear, thorough engineering documentation and communicate design decisions effectively.

we are looking for a phenomenal engineer to join the chip simulation team for networking chips and gpus. this simulation platform enables engineers across firmware, sdk, and os domains to develop and TEST their code without relying on physical hardware. if you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.
what youll be doing:
develop and maintain simulation infrastructure components for different simulation teams (gpus, switches, nvlink, ethernet, phy) of high-performance networking chips.
define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded ipc mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.
own, extend and optimize all the ci/cd of the simulation team, starting from servers installation to adding and maintaining various jenkins jobs that help Developer and improve their life.
collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.
support internal users by debugging simulation flows and collaborating on bug resolution.
take part in future-facing innovation by enabling simulation for next-generation devices and features.

Key job responsibilities
Develop and design advanced semiconductor technologies for cloud infrastructure.
Collaborate on architecture definition and logic design for next-generation computing platforms.
Participate in comprehensive chip verification and bring-up processes.
Contribute to the entire product lifecycle from initial concept to mass production.
Support integration of new chip designs into AWS data center environments.

Nuvoton Israel is a leading supplier of SoCs, microcontrollers and security hardware solutions for tier-1 customers in the computing and server business. A self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production. Our products combine unique sets control, management, and advanced security solutions, enabling our customers to establish differentiation in their end markets. We are looking for a Chip Design Verification engineer to join our Verification team! This is your opportunity to have an impact on the design of millions of computers sold worldwide each year by leading brands.
The role includes: - Building complex verification environments - Meeting the challenges presented by state-of-the-art design - Continues professional growth using the most advanced tools and methodologies - Use AI for improved productivity

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

what you'll be doing:
you will take engineering ownership of networking products once they are released to production
provide engineering technical leadership for improving product availability, driving cost reduction, and resolving manufacturability issues
work on debugging and resolving hw related quality issues to improve customers' satisfaction

looking for an experienced electronics/ system Engineer to serve as a technical project leader (tpl), join our organization, and be a part of the system product engineering organization. the team delivers brand new, high-quality products to nvidia's customers, applying the following: development and deployment of automatic testers for nvidias network business units (computing network adapters and high-speed switch systems) including hardware, software, and mechanics; coordinating and leading all aspects of the analysis of manufacturing data to identify and mitigate quality issues using advanced data analysis techniques such as Machine Learning, statistical tools, and ai; leading smooth production and capacity enlargement and failure analysis of return material from customers to understand the reason for failures ;validating TEST performance and stability using QA (v&v - validation and verification) methods; the tpl leads projects from requirement until end of life; engineering manager for spe projects and technical authority across spe teams
what youll be doing:
building integration plans, communicating status and priority among the teams (in/outside of spe), assessing risks and developing mitigation plans
leading the project lifecycle in the spe group, which starts at the requirements stage, through chip design and fw stages till spe mp, including quality and yields improvement plans
responsible for bugs management prioritization and tracking and relevant knowledge transfer to the spe group
working closely with development teams for environment improvements, such as automation, and driving mitigations to reduce risks
collaborating with pm for schedule tracking and modifications
evaluating new technologies and testing capabilities for improvement
working with the testing architecture team (dft) to assure testing setups and coverage are met
engaging with a variety of teams: r&d, hw and sw, chip design, operations, thermal, signal integrity, fw and sw, layout, and more, report project status for high level management

Your role:

Design, implement, integrate, and test a (sub)system, component, or module in high quality, according to requirements and on time.
Comply and align with software development professionalism standards within the team (processes and methodologies, quality of requirements, design, coding, and testing).
Carry out complex development and prototyping tasks.
Understand market needs and translate them into implementation requirements while considering the overall solution.
Work on multiple projects, including new product life cycle development as well as maintenance of already released products.
Promote domain knowledge, innovative thinking, and customer understanding.
Promote trust and openness, and leverage external capabilities locally and globally.
A career at Philips comes with all sorts of wonderful benefits. Be sure to speak to your recruiter about benefits in your region.

we are looking for an experienced engineer with a strong background in asic design to join our chip design methodologies team based in tel aviv and yokneam. this team is responsible for establishing asic design methodologies, developing shared code, providing design guidance, and driving the adoption of new technologies. it plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. this role offers an exciting opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.
what you'll be doing:
develop ground-breaking methodologies and innovations to create flawless experience in chip design development
utilize, develop and assimilate ai-based tools and flows
collaborate with chip design stakeholders and peers across the teams to understand existing problems and form the best solutions and methodologies
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our development process
develop training sessions and guide designers with best design practices
develop shared design code and solutions to be widely used by the chip design team

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

This position can be located in Haifa or Hod HaSharon
Be part of a team responsible for designing the next generation of mobile devices. The position includes responsibility for system analysis and SW/HW architecture design for high-speed and low-power interfaces, networking algorithms, or audio processing. This job requires a collaboration with multiple engineering teams in various geographical locations to define requirements, interfaces, interaction between SW and HW blocks, performance analysis, and more.