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We are seeking a CAD Engineer to join our team. In this role, youll contribute to the development and automation of flows, tools, and methodologies (TFM) in the backend power domain as well as at the architecture and micro-architecture levels. This is a cross-functional role that blends software engineering excellence with deep insight into chip development processes.
Success in this role requires strong communication skills, a creative and data-driven mindset, and a passion for delivering high-quality results.
What youll be doing:
Develop and support tools flows and methodologies in backend power design of networking chips and SOCs .
Collaborate with backend engineers, architects and micro architects to support and improve design process.
Be responsible for the full lifecycle of tool development from design (data storage and UI) to testing, deployment, and maintenance.

As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

As a CPU Workload Analysis Researcher within Google Cloud's MSCA organization, you will be integral to developing silicon solutions powering Google's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the Google Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of Google users and Cloud customers.

Responsibilities
Plan and execute detailed analysis of CPU workloads within the Google Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on Google Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

Our Autonomous Driving Software Group in Jerusalem is looking for an experienced C++ developer to join our team!
Our group is responsible for developing new ethernet switch architecture and tools to replace existing code with a modern, scalable design.
We enable support for new design wins and help scale our technology to run efficiently in vehicles, contributing to saving lives and enabling autonomous driving.
What will your job look like?
Take part in designing and developing large-scale network applications running on our cutting edge platforms which have our industry leading EyeQ chip.
You will work on a complex real-time system involving multiple sensors as part of a broader automotive system architecture.
The main application is developed in C++ for Linux environments.
You will develop advanced simulation software used company-wide, integrating the latest technologies.

In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.

We are looking for a Product & Test ATE Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will be responsible for performance analysis for an end-to-end networking stack using your infornation of RDMA based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

Our Autonomous Driving Software Group in Haifa is looking for an experienced C++ developer to join our team!
Our group is responsible for developing new software architecture and tools to replace existing code with a modern, scalable design.
We enable support for new design wins and help scale our technology to run efficiently in vehicles, contributing to saving lives and enabling autonomous driving.
What will your job look like?
Take part in designing and developing a large-scale application from scratch.
You will help build a massive simulation farm running on our EyeQ chip to overcome the inefficiencies of machine learning simulations on x86 platforms.
You will develop advanced simulation software used company-wide, integrating the latest technologies.
You will work on a complex real-time system involving multiple sensors as part of a broader automotive system architecture.
The main application is developed in C++ and Python for Linux environments.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for a networking stack using the knowledge of Remote Direct Memory Access (RDMA) based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.
Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.
Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.
Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.
Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.
Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.
Develop SoC test and calibration capabilities for chip, module, and product factories.
Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes.

Required Senior Computer Vision - Algorithm Engineer
The Surround-Perception group is dedicated to solving advanced vision problems, with a focus on 3D domain encompassing reconstruction and object detection. Our team research, develops, and deploys cutting-edge techniques to achieve world-class results, contributing to the safe advancement of Autonomous Driving.
What will your job look like:
Conduct research and develop innovative Computer Vision and Deep Learning algorithms in areas such as Object Detection and Tracking, Depth Sensing, and 3D Reconstruction.
Engage in cutting-edge Computer Vision projects, from the data science and research stages, through proof of feasibility to the deployment of solutions.
Performance-oriented deployment of Computer Vision and Deep Learning algorithms on a Real-Time embedded chip for autonomous driving.
Collaborate with engineering and research teams in Computer Vision, Machine Learning, and Data Engineering to solve real-life problems.
Continuously learn and stay updated on the latest advancements in relevant research fields that impact our daily work.

In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

In this role, you will work with internal system teams and the System-on-Chip (SoC) Architecture team to develop an understanding of the SoC, performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model SoC performance at different accuracy levels by supporting architectural explorations and decision-making. In addition, you will correlate performance projections with measured post-silicon data.

Responsibilities
Develop simulators and architectural models of general-compute SoCs.
Collaborate with system architects, SoC and IP architects/designers, and software and application experts to understand current and future requirements.
Participate in architectural and design evaluation of SoC designs.
Perform pre-silicon performance simulation and correlate with post-silicon measurements.
Communicate analysis results qualitatively and quantitatively.