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DFT Intern - ASIC Student - Israel - ETR
Job Description
Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a representative may contact you directly if a relevant position opens.
Who We Are
The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.
The ideal candidate is friendly, social, easygoing, with a good sense of humor, and has the ability to learn independently. They should be located in central\north Israel (Tel-Aviv\Caesarea). Strong independent work skills and job stability are important.
What You'll Do
Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing.
Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

We are seeking a visionary and results-oriented Hardware Group Director to lead our hardware department.
In this role, you will be responsible for the end-to-end hardware development life cycle, from initial architecture and high-level design to mass production and field support. You will lead a multidisciplinary team of engineers, including mechanical, electronics, motion, and hardware experts, driving innovation while ensuring high-quality execution, on-time delivery, and alignment with company business goals.
What will you be doing:
Technical Leadership & Strategy
Define and drive the hardware technology roadmap and architecture for next-generation products.
Lead critical design reviews to ensure engineering excellence and minimize design iterations.
Identify and evaluate emerging technologies and vendors to maintain a competitive edge.
Oversee DFx (Manufacturing, Testing, serviceability) to ensure seamless transition from R&D to production.
Team Leadership & People Management
Build, lead, and mentor a high-performing multidisciplinary team across electronics, motion, and mechanical engineering.
Foster a culture of innovation, collaboration, and continuous professional growth.
Drive resource planning, project allocation, and performance management processes.
Lead recruitment efforts to attract and retain top-tier engineering talent.
Project Execution & Operations
Own the end-to-end hardware project lifecycle, ensuring on-time delivery and alignment with budget and quality targets.
Manage relationships with key suppliers and global manufacturing partners.
Oversee departmental budgets, lab infrastructure, equipment procurement, and EDA tool strategy.
Ensure compliance with global regulatory and quality standards.
Cross-Functional Collaboration
Lead a matrixed hardware group supporting multiple product lines and engineering domains.
Serve as the primary technical interface to executive leadership, providing clear visibility into progress, risks, and mitigation plans.

Required Post-Silicon Validation Engineer
About The Position
We build cutting-edge radar chipsets for next-generation automotive sensing systems. As a Post-Silicon Validation Engineer, you will play a critical role in bringing complex mixed-signal ICs from silicon to system readiness.
Responsibilities
Perform validation of advanced radar ICs from bring-up through full functional and performance testing
Translate system and chip-level requirements into comprehensive validation plans and test cases
Develop automated test environments using lab instrumentation and custom scripts
Execute silicon bring-up and validate key subsystems (clocking, power, CPU, interfaces, sensors)
Perform electrical and parametric validation, including high-speed, power, and interface testing
Run characterization across PVT conditions and analyze large datasets
Debug complex silicon issues and work closely with design, verification, and system teams
Support device readiness for system integration and productization.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team:
Our team builds firmware, SDKs, simulators, and compilers for the Silicon One architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

We are looking for an excellent design engineer to join our team and build our company's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface.

We are looking for an Experienced HW SERDES Engineer to join Annapurnas SPIV (System Platform Interface validation) team.
As a member of the SPIV team, you will own End-to-end subset of system PCIe SERDES interfaces across range of products through product life cycle:
1. Validation and qualification.
2. Integration.
3. Deployment and post-deployment support.
4. Failure analysis.
5. Pre silicon activities for new technologies.
As owner, you will set the strategy for PCIe SERDES qualification over multiple platforms, ensure the design worked well and drive complex system debugs involving HW and FW components.

You will define NPI practices and engage in pre-silicon efforts to explore new technologies and mitigate integration risks. You will enhance SERDES qualification results with large scale customer performance analysis to discover SERDES life-cycle issues and mitigate them.

This is a fast-paced, intellectually challenging position, and you will work with thought leaders in multiple areas of technology. We are changing industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities
- Approve future products PCIe SERDES technologies.
- Define new products SERDES qualification and validation strategy and lead the execution.
- Engage integrations of Annapurna Labs products with other vendors PCIe HW components.
- Support ongoing integrations of PCIe SERDES in new products.
- Lead triage, PCIe SERDES debug and root cause analysis of systems in AWS data centers.
- Drive and maintain training, quality documentation and collateral to improve in-fleet operation.

Required PHY Post Silicon Validation Engineer
Job Description
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Silicon One group as part of the silicon development.
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Who You'll Work With
You'll be part of our Group driving our game changing next generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.
Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

our company Autonomous Driving software group is looking for a Linux kernel expert with deep knowledge in the PCIe standard. As a Linux Kernel PCIe Architect, you will be part of the OS Architecture team and will be responsible to define the operating system solutions based on the PCIe standard for connectivity with peripherals and as an interconnect between multiple EyeQ SoCs.
This is an exciting and unique opportunity to work with highly talented Linux OS architecture and developments teams and be a leader in the definition of the cutting-edge technology for the Automotive AI applications.
What will your job look like?
Researching and defining the SW solutions based on the PCIe standard and the Linux implementation for the PCIe stack
Designing and Implementing the SW Stack for the communication between the EyeQ SoCs laying the infrastructure for cross chip neural networks.
Defining the future HW solutions by working closely with the SoC Architecture team in a SW/HW co-development environment.
Performing performance analysis, feasibility studies, PoCs and optimization flows to achieve the highest performance with minimal resources.
Work closely with the Linux Kernel team and provide the technical guidance and mentoring for development engineers.

our company Autonomous Driving software group is looking for a Linux kernel expert with deep knowledge in the PCIe standard. As a Linux Kernel PCIe Architect, you will be part of the OS Architecture team and will be responsible to define the operating system solutions based on the PCIe standard for connectivity with peripherals and as an interconnect between multiple EyeQ SoCs.
This is an exciting and unique opportunity to work with highly talented Linux OS architecture and developments teams and be a leader in the definition of the cutting-edge technology for the Automotive AI applications.
What will your job look like?
Researching and defining the SW solutions based on the PCIe standard and the Linux implementation for the PCIe stack
Designing and Implementing the SW Stack for the communication between the EyeQ SoCs laying the infrastructure for cross chip neural networks.
Defining the future HW solutions by working closely with the SoC Architecture team in a SW/HW co-development environment.
Performing performance analysis, feasibility studies, PoCs and optimization flows to achieve the highest performance with minimal resources.
Work closely with the Linux Kernel team and provide the technical guidance and mentoring for development engineers.

The Imaging and Sensing group develops Depth and Image Sensing systems, including the groundbreaking True Depth camera that powers FaceID and the recently released LiDAR scanner.
This multidisciplinary team of ground breaking engineers is responsible for the architecture, design, development, and validation of these highly complex sensing systems, tailored for our products.

We are looking for a student position to join our caSystem Validation team to collaborate on advanced electro-optical system development.


Contribute to a core technology team designing, developing, and validating advanced solutions for our future products.

Conduct characterization, test, and validation aspects of our cutting-edge sensing systems, spanning from early lab prototypes to complete system maturity.

Design and implement complex lab-based experiments, followed by thorough analysis supported by simulations.

Develop and execute lab automation for products evaluation.

Conduct data-driven analysis to support decision-making processes.

We build flexible, secure, and scalable payment solutions that improve cash flow and reduce friction in complex financial workflows.

Were looking for a Product Designer who brings strong craft, product intuition, and ownership. Youll take the lead on meaningful product areas, shape experiences end-to-end, and partner closely with Product and Engineering to deliver high-impact solutions.

Responsibilities
Own design for key product areas-from discovery to polished execution
Act as a thought partner in shaping product direction-not just executing on specs
Partner with Product Managers and Engineers to define problems, shape strategy, and deliver impactful solutions
Turn complex financial workflows (e.g. payments, reconciliation, approvals, credit flows) into simple, intuitive, and scalable experiences
Lead design processes including research, ideation, prototyping, and validation
Use qualitative and quantitative insights (user research, analytics, experiments) to guide decisions
Design with clear success metrics in mind (adoption, conversion, efficiency, revenue impact)
Create high-quality UX/UI deliverables: flows, wireframes, and high-fidelity designs
Contribute to and evolve our design system to support scalability across complex product surfaces
Work closely with engineering to ensure high-quality implementation and thoughtful trade-offs
Raise the bar for design quality through feedback, critique, and collaboration
Explore and integrate AI into product experiences and internal design workflows where it meaningfully improves outcomes