לוח משרות דרושים

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our portfolio spans CPU, TPU, Networking and other key data center technologies, which power our company's most demanding Compute and AI/ML applications.
In this role, youll work to shape the future of strategic Data Center silicon. Youll be an early and key contributor in a nascent high-growth team that pushes boundaries, developing advanced custom IP and solutions. You will need expertise in one or more of the following areas: wireline communications, analog circuit design, Digital Signal Processor (DSP) design and algorithms, signal integrity, transmission line theory, advanced analog and mixed-signal modeling, high-speed clocking, Clock and Data Recovery (CDR), equalization, high-speed input/output (IO) industry standards. Your role has a significant component of cross-collaboration with a broad set of cross-functional organizations. You'll bring out the best in the team to deliver designs that serve many of our companys advanced data center products.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Architect and design high-speed analog/digital circuits (ADC, DAC, PLL, CDR, DSP), including optimizing for Power, Performance, and Area (PPA).
Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
Bring up new silicon, characterize performance, and test for electrical compliance in lab environments.
Work with packaging, board design, and firmware teams to ensure seamless integration into System-on-Chips (SoCs).
Adhere to standards like IEEE or OIF for high-speed protocols and optimize power consumption.

we are looking for a VLSI Design Engineer.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs. This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:

Develop and maintain simulation infrastructure components for different simulation teams (GPUs, switches, NVLink, Ethernet, PHY) of our high-performance networking chips.

Define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded IPC mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.

Own, extend and optimize all the CI/CD of the simulation team, starting from servers installation to adding and maintaining various Jenkins jobs that help developer and improve their life.

Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.

Support internal users by debugging simulation flows and collaborating on bug resolution.

Take part in future-facing innovation by enabling simulation for next-generation devices and features.

Our New Product Introduction (NPI) team is growing, and We are now looking for a Chip Engineering Operations Program Manager! The Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the silicon schedule from bring-up to production release. We are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. We desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. You will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. You will also review and improve processes, and handle prototype demand.

What you'll be doing:

You own silicon bring-up schedule from power on to production release.

Negotiate silicon and board demand with teams and drive a bottom-up forecast.

Oversee and manage chip and board allocations across the company.

Lead prototype chip delivery to internal customers.

Track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase.

Identify and mitigate risks to schedules and programs.

Communicate status to cross-functional teams as well as upper management.

Continuously evaluate internal tools and processes and drive fixes to improve productivity.

Create new and fix existing processes between different teams.

Drive implementation of SW tools for data analytics and process evaluation.

We are looking for an experienced, forward-thinking, focused, analytical, and motivated Engineer to take ownership for the NPI and suppliers management in order to meet company targets. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which NV products acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. Youll be immersed in a diverse, supportive environment where everyone is encouraged to do their best work. Come join the team and see how you can make a lasting impact on the world.

What you'll be doing:

The NPI engineer will work alongside with R&D BU, finance, engineering and various multi-functional teams, leading NPI products from am operational perspective.
Work with our partners worldwide to establish a supply chain incorporating business, manufacturing, technology, Engineering, quality, and additional aspects to assure design acceptance and manufacturability
Identify critical-paths, bottlenecks and implement risk management methodologies.
Define and lead execution to ensure delivery on schedule according to SOW and budget.
Pave the way for NPI Production transition: Active participation from very early pre-design stages, highlighting needed operational related aspects while defining the infrastructure for the future transfer to production stage.
Develop an in-depth understanding of the vendors manufacturing capabilities and influence current and future product qualifications and loading decisions
Develop and implement project management methodologies and processes to improve tracking, transparency, execution, and day-to-day efficiency
Report program status to senior management.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help build SoCs by driving quality and reliability processes from the Integrated Circuit (IC) perspective. Working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute test plans. Within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. You will have an understanding of IC flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.
The ML, Systems, and Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and lead qualification hardware and test developments in front of internal teams and external vendors.
Define and execute Silicon and package qualification activities (e.g., HTOL, ELFR, ESD/LU, b/HAST, THB, etc.).
Extract, manipulate, and analyze large volumes of data from Silicon and package qualification programs (e.g., HTOL, ELFR, ESD, LU, UHAST, TCT, etc.), High Volume MFG, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
Own cross-functional investigation of IC quality and reliability issues to identify root causes and develop solutions (e.g., RMA Triage, Analytics, Failure Analysis, etc.).
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, TDDB, NBTI, HCI, Time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin Cisco's future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

Join the PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.

We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.

Your Impact:

Develop PHY firmware and system-level features for advanced networking ASICs.

Design and implement PHY calibrations and system definitions.

Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis.

Collaborate closely with PHY, system, firmware, and silicon design teams.

Contribute to defining system operation modes and end-to-end device behavior.

Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies.

What youll be doing:
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all our business units (GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI), all using Cadence PCB design tools.
Focus will be on the complete development of CAD layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity.
You will be responsible for the design releases required generation of artwork files, ODB++, and electronic PCB documentation.
Your designs will need to follow SI constraints, EMI/RFI control and FCC, UL and European regulations, IPC specifications and NRC regulations.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Participate in test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Were looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASIC-from initial concept to final production. In this pivotal leadership role, you will own the full ASIC lifecycle, drive execution across global teams, and partner with cross-functional stakeholders to deliver cutting-edge silicon that shapes the future of autonomous vehicles.
What Youll Do
Own and lead the end-to-end ASIC development process
Serve as the central point of contact for all ASIC-related activities across Product, Firmware, Computer Vision, Hardware, and R&D stakeholders
Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams
Define and enforce VLSI development methodologies, design flows, and quality standards
Evaluate, select, and integrate both digital and analog IPs required for the ASIC
Manage relationships and deliverables with external VLSI partners and service providers
Ensure high-quality execution, risk management, and delivery across all project phases.

In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure and project execution for the next generation MSP (Memory Signal Processing) IPs to enable state of the art storage solutions for Apple products line.
Description
You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus in UVM.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design, architecture, software, system and validation teams from the early stages of IP definition, to ensure timely delivery of quality designs.
Involvement with Post Silicon Validation and other verification teams.

The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.

we are looking for a senior pcb design layout engineer to join our hardware engineering team at the autonomous vehicle platform department as a key player in the development of next-generation ecu (electrical control unit) for autonomous vehicles. what will your job look like?
working closely with hardware and mechanical design engineers, you'll perform pcb layout our ecus and other products.
complete development of cad layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
be responsible for the design releases required generation of artwork files, odb++, fab drawings, ict report, and electronic pcb documentation.
your designs will need to follow ipc class 3, signal and power integrity constraints, emi/rfi control and automotive regulations.

As a part of the R&D mechanical team you'll lead and design the required solutions for a high-end Wireless charging system. From the stages of concept definition to successful implementation. You'll have full ownership of the mechanical design, including analysis, testing, manufacturing, validation and integration. you'll collaborate with cross-functional design teams such as hardware, electronics, and software.
And you will be an integral part of a dynamic environment with great team energy.

Your role involves providing support for production and ensuring compliance with deadlines, quality and cost targets.