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We are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of our future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist.
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts.
Leading processes relating to power optimization.
Technology expert, building a knowledge base for the group.
Work with various teams to drive execution (SW, Architecture, verification, BE, etc).
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

We're looking for exceptional engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle. Verification in our company isn't a downstream checkpoint - it's the connective tissue that spans the entire product journey:
It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written
It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack
It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality
It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development
What sets us apart:
Agentic AI is embedded in our workflow - not as an experiment, but as a core part of how we design and verify chips.
Cutting-edge methodologies drive every stage of our verification process
Relentless innovation - we don't settle; we actively seek new approaches that raise the bar on silicon quality.
We do classic functional verification(SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality.
Performance optimization at all levels it is at the heart of our targets on top of logical correctness verification.
If you want to be at the nerve center of chip development - where your work connects every discipline and powers the backbone of AWS Graviton - this is your team.

Required Performance Architect
Job Description
What You'll Do
Join our Silicon One architecture team, the core of silicon development. Our architects manage all aspects of system chip development and provide specifications to various development teams. In this role you will:
Define the features and specifications of future devices.
Utilize a data-driven approach to model and analyze networks of tomorrow, providing optimal solutions for our customers.
Model, analyze, and present simulation results for cutting-edge networking solutions across various use cases.
Apply strong networking research skills and a robust theoretical background to your work.
Who You'll Work With
You will be part of our Silicon One architecture team, which is central to our ASIC group.
Our team, which operates with a startup mentality within a stable and leading corporation, drives the development of next-generation networking devices-Silicon One.
Our design center is unique, hosting all silicon hardware and software development disciplines at one site. We are revolutionizing the industry by building a new internet for AI networks and the 5G era, with a unified, programmable silicon architecture that will underpin all of our future routing and switching products.
Our devices are engineered to be adaptable across service providers and web-scale markets, designed for both fixed and modular platforms. They deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility. Silicon One is set to be a transformative technology for decades to come.

Required PHY System
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

Required Senior Electrical Post Silicon Validation- Silicon One
Job Description
Meet the Team
We are a dynamic group of engineers dedicated to pushing the boundaries of technology. Our mission is to validate and drive the performance of Silicon One products, ensuring they meet the highest standards of quality and reliability.
Operating at the forefront of technology, we work with latest, high-speed, and power-hungry devices. Our small, but highly influential team thrives in this challenging environment, applying our expertise to impact the future of networking technology. With a commitment to excellence and a passion transformative technology, we are shaping the future of high-performance Networking and delivering unparalleled value in every project we undertake. Join us, and be a part of a team where professionalism meets impact!
Your Impact
Drive the resolution of complex silicon performance and characterization issues through deep, multi-functional collaboration with architecture, design, and software teams. Leverage these technical insights to provide critical feedback that directly influences the design, debuggability, and architectural specifications of future silicon components
Key Responsibilities:
Lead the Electrical Post Silicon Validation efforts for Silicon One products, focusing on high-speed and power-intensive devices. Collaborate with multi-functional teams to drive the silicon validation process, from architecture through to physical design and DFT. Analyze and interpret characterization data to guide design improvements and ensure product excellence. Develop and execute test plans to validate silicon performance and reliability against stringent specifications. Troubleshoot and resolve issues related to silicon performance and characterization.
Why Join Us:
Be part of team at the forefront of silicon technology, working on the most advanced products in the market. Work closely with some of the best engineers in the industry, driving innovation and excellence in silicon characterization. We are a fast growing team that values talent and provides ample opportunities for professional development and career advancement.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

We are looking for a Photonics Layout Engineer to join our integrated photonics design team.

This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.

In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules.

You will work closely with device designers, process engineers and tape-out teams to deliver high-quality layouts of silicon photonics PICs.

Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software.

Understanding of photonic components, waveguide routing and automated layout generation is a major advantage.

You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.

Responsibilities

Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software.

Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.).

Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths.

Verify layouts using DRC, and LVS to ensure compliance with foundry requirements.

Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts.

Optimize layouts for performance, yield, and compactness while adhering to technology constraints.

Participate in photonic design automation tool development and workflow improvements.

Prepare and manage data for tape-out and support mask review processes.

Debug layout and rule-check issues and propose corrective actions.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team:
Our team builds firmware, SDKs, simulators, and compilers for the Silicon One architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
Silicon One is at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

Which department will you join?
Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Required Software Post Silicon Validation Lead
Job Description
Meet The Team
Welcome to the Post-Silicon Validation Team at Silicon One , where startup energy meets the scale of a global technology leader.
As part of Silicon One Group, we help deliver the silicon, optics, and hardware platforms behind our core Switching, Routing, and Wireless products used by enterprises, service providers, public sector, and non-profit organizations worldwide.
Our team works side by side with verification engineers, designers, and cross-functional partners to validate complex ASICs across their full lifecycle and ensure outstanding product quality.
At the center of this innovation is Silicon One, the industrys only unified silicon architecture, powering platforms from Top-of-Rack switches to web-scale data centers and critical AI infrastructure.
Your Impact
Lead validation work for complex networking ASICs, from first silicon bring-up to production.
Manage and support a small validation team, and guide daily technical work.
Own the validation plan for features, performance, power, and reliability.
Find and solve issues across silicon, firmware, drivers, and system software.
Work with architecture, SDK, and firmware teams to improve product quality, stability, and test coverage.
KEY RESPONSIBILITIES:
Lead post-silicon validation and debug for networking ASIC projects.
Manage tasks and technical direction for a small validation team.
Build and run validation plans for function, performance, power, and reliability.
Drive silicon bring-up, stepping checks, and production readiness.
Develop validation tools and automation using C/C++ and Python.
Run stress and long tests to find hidden silicon problems.
Debug hardware and software issues in the lab.
Validate networking features and interfaces (for example Ethernet, PCIe, SerDes, DDR, SPI, I2C, UART).
Add tests to regression flows and track progress until closure.
Document results, issues, and recommended fixes clearly.

We are seeking a Technical Project Manager with proven expertise in High-Speed Board Design and hardware project management to join our Firewall Core Group. This role involves leading complex, cross-functional projects that combine hardware and software, driving innovation for our company Security Gateways.
Key Responsibilities
Lead hardware/software projects from planning through delivery.
Manage board design, hardware development, and prototype builds (EVT, DVT, PVT) with contract manufacturers.
Coordinate across R&D, QA, PMO, and Product Management teams.
Oversee software release processes and infrastructure changes.
Maintain schedules, mitigate risks, and manage external vendors.

What youll do:
Lifecycle Ownership: Lead projects from concept through research, execution, and iterative improvements.
Design Leadership: Lead by example, providing mentorship, guidance, and fostering a collaborative and creative environment.
User-Centered Validation: Strategically apply user research, prototyping, and usability testing insights to define and validate high-impact design solutions.
Design Excellence: Drive the creation of high-quality, visually appealing, and functional designs for web, mobile and our back-office platforms.
Cross-Functional Partnership & Strategy: Partner with cross-functional teams and functional leads to align design strategy with business objectives and product goals, delivering innovative features and enhancements.
Process Improvement & Innovation: Continuously elevate design efficiency by championing new methodologies, integrating cutting-edge tools, and streamlining the design-to-development workflow.

Were looking for a creative, strategic, and detail-oriented Product Designer to help shape the future of all-in-one Remote Monitoring and Management (RMM) platform- now evolving into Autonomous IT.
Youll design the system end-to-end: from the core monitoring, management, and reporting tools IT pros rely on every day, to new AI-powered capabilities like Autopilot IT and Copilot that extend their reach and speed. Your work will help IT pros and the employees they support unlock a new era where IT runs itself-smarter, faster, and always in control.
What Youll Do:
Lead design projects across the full RMM system, from foundational workflows to AI-enhanced features.
Own end-to-end design: research, ideation, interaction design, prototyping, and developer handoff.
Design cohesive platform experiences- ensuring AI agents feel like natural extensions of the tools and systems IT pros already use.
Collaborate cross-functionally with PMs, engineers, UX writers, and researchers to define problems and co-create solutions.
Advocate for the user by applying UX best practices, accessibility standards, and data-driven decision-making.
Apply our design system to create consistent, high-quality experiences across the platform.
Communicate design rationale clearly to stakeholders at all levels.
Iterate rapidly on feedback and usability findings, balancing speed with quality.