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Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

Required Staff Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead end-to-end signal integrity definition, channel budgeting, and stackup optimization for complex multi-die packages, including 2.5D (CoWoS, EMIB, InFO), 3D vertical stacking, and high-density organic substrates.
Architect and optimize multi-terabit interconnects across Die-to-Die (UCIe/BoW), host links (PCIe Gen6/7, PAM4/# SerDes), and memory subsystems (HBM3/4, DDR5, LPDDR6) in close collaboration with PHY and silicon design teams.
Build high-accuracy 3D full-wave electromagnetic models (HFSS) for micro-bumps, C4 bumps, TSVs, interposers, and BGA transitions, establishing automated flows for statistical eye/BER margin analysis.
Define high-frequency test vehicles, fixtures, and measurement methodologies; execute multi-port VNA, TDR, and real-time scope characterizations to correlate lab measurements with predictive simulations.
Collaborate closely with Silicon Design, Package Layout, Board/System, and external foundry/OSAT partners to resolve design trade-offs

Were looking for a Design Manager to join our collaborative team in Israel and support the delivery of complex semiconductor projects. Youll lead and coordinate multidisciplinary design activities, working with engineering, architecture, construction and client teams to develop designs that meet project requirements and can be delivered safely and effectively.
Youll guide design development from early planning through construction, helping teams coordinate interfaces, manage design schedules and deliver high-quality technical information. Youll work closely with clients, our colleagues and external consultants to resolve design issues, manage changes and support the transition from design into construction.
This role also includes involvement during construction, helping address design-related queries, review technical submittals and resolve issues that arise on site. Its an opportunity to contribute to high-profile semiconductor projects while developing your experience alongside a skilled, multidisciplinary team.
Key responsibilities:
Lead and coordinate multidisciplinary design activities across engineering and architectural disciplines.
Coordinate internal design teams, specialist consultants, and client stakeholders to deliver integrated design solutions.
Manage design scope, deliverables, interfaces and schedules in line with project requirements.
Facilitate design reviews, identify technical risks and support timely resolution of design issues.
Maintain effective communication between design teams, clients, construction teams and other stakeholders.
Support the development and coordination of design documentation, specifications, estimates and proposals, as required.
Monitor design progress and provide clear updates on status, risks, decisions and required actions.
Support construction-stage activities by responding to design queries, reviewing technical submittals and coordinating design clarifications.
Help ensure design solutions meet applicable codes, standards, quality requirements and our health, safety and environmental expectations.
Promote our policies, procedures and values across project activities.
This list is not intended to be all-inclusive and may be expanded to include other duties and responsibilities.

Semi Conductor Devices (SCD), a worldwide leader of high-end Infrared Detectors and thermal video cores, is seeking a Senior Digital VLSI Engineer to participate in the definition, design, verification, implementation, and silicon validation of next-generation infrared image sensors. Responsibilities • Be part of a team defining future Image Sensor Digital controller Architecture • Participate in the digital design and verification effort of state-of-the-art IR Image Sensors, working closely with the Analog designers and Board designers (internal and external interfaces) • Take part in ASIC development lifecycle (pre- and post-silicon) – from Spec definition to block-level design, full-Chip till Silicon Validation in the laboratory and customer support • Lead the design and integration of complex digital blocks from specification to silicon • Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.

The team leads the development of networking infrastructure for NVIDIA's next-generation data centers, focusing on accelerated performance while enabling optimized end-to-end GPU connectivity, focusing on datacenter-level optimized solutions for AI.

As a leader of our switch Hardware Engineering team, you'll guide, encourage, and drive a team of highly skilled hardware engineers, providing them with stimulating and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.

What You'll Be Doing:

Build the best team to design and execute high-performance switch system from concept to mass production.

Be a key member of the technical leadership team developing world-class switch designs.

This position is hands-on and will require a deep understanding of all technical/engineering aspects of the project with intimate familiarity with the entire development flow. From a technical standpoint, you will lead and support engineering teams in the following areas: specification definition, electrical schematics, opto-mechanical design, component selection, layout guidance, hands-on lab testing, production processes, qualification workflows, micro-architecture development, verification, characterization, design for testability, cost optimization, reliability, and more.

Collaborate with and integrate all HW project disciplines: Board Design, Assembly Process, Mechanics, Thermal, PCB Layout, Process , Production Engineering, Software/Firmware, Procurement, NPI, and more.

Plan and oversee your teams work on multiple simultaneous development projects in coordination with the broader leadership team. Manage direct reports, set goals, provide coaching, conduct performance appraisals, plan careers, and make compensation recommendations.

Collect, examine, and filter requirements from internal customers such as marketing, software, and systems engineering to assemble a comprehensive plan of record for next-generation switches while planning resource allocation for projects and assign team members effectively.

Schedule projects, create realistic outcome estimates, and drive timely, successful execution for high-volume manufacturing.

Required Senior Edge-AI SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for application-specific integrated circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, memory built-in self test (MBIST), and automatic test pattern generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

Required Networking Silicon Architect, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a part of the team, you will define solutions for high-performance network accelerators and interconnects in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, with close collaborations with data center systems and Software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center networking infrastructure.
You will be responsible for performance analysis for an end-to-end networking stack using your deep knowledge of high speed network infrastructure.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate different silicon solutions for executing our data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and advanced silicon integration technologies.
Design high-performance hardware/software interfaces.
Collaborate closely with system, software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Drive vendor execution in various engagements: standard component roadmaps, build to specification, and co-developments.
Contribute to the evaluation of future ASIC designs and general architecture.

We are looking for an experienced hardware design engineer to join our team.
In this position, you will be responsible for the product hardware starting from the concept phase and turning it into a stable and reliable product to be used by our customers.
Primary Duties:
Design of New Application processors/SoCs (NXP, TI, etc.) based boards (System on Modules) and related products.
Board design and layout.
Support board bring-up of new platforms.
Documentation of designs is your responsibility.
Supporting end-customer through module integration.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As our Product Designer, you will own our entire visual landscape. You will lead the design of our core platform, turning complex engineering data into intuitive interfaces, while also acting as the creative lead for our brand. Whether you are building a scalable design system for the product or designing high-fidelity demos and marketing materials, you will be responsible for the functional and visual standards across the entire company.

What youll do
Own the Experience: Lead design, shape how people experience , from product to brand, so every interaction feels simple, human, and intentional.
Simplify the Complex: Turn dense supply chain data and technical datasheets into intuitive, "magical" interfaces that engineers actually enjoy using.
Rapid Prototyping: Use modern tools (Figma, Lovable, Cursor) to move from a whiteboard sketch to a high-fidelity prototype in hours.
Drive Brand Identity: Evolve visual language across product and marketing. Keep it consistent, sharp, and never boring.
Work with Builders: Collaborate closely with founders, engineers, and users to solve real frustrations. Validate ideas through research and continuous feedback.
Design Storytelling: Use design to power customer demos and pitches, turning our vision into a compelling narrative that wins over users and investors.
Turn Insight into Decisions: Conduct user research and testing to inform what we build, and what we dont. Keep us grounded in real needs, not assumptions.

We are looking for a Design System Tech Lead to lead the evolution of Design System into a modern, scalable, and AI‑ready frontend platform.
This role focuses on platform ownership, not feature development. You will be responsible for improving how designers, developers, and tooling (including AI tools) build consistent, high‑quality user interfaces across the company.
What youll do:
Lead the modernization and technical direction of the Design System.
Own component architecture, design tokens, theming, accessibility, and performance.
Improve developer and designer adoption by reducing friction, improving documentation, and simplifying upgrades.
Make the Design System machine‑readable and tool‑friendly, enabling automation and AI‑assisted development.
Define quality standards, testing strategy, and governance for Design System changes.
Work closely with product design, frontend teams, platform, and DevOps partners.
Mentor engineers and contribute to frontend platform best practices.