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Requred SoC Power Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.

Required Analog Design Engineer
Job Location:
Israel, Hod HaSharon (Hybrid)
Job Brief:
Be part of the team that is responsible for developing and optimizing the state-of-the-art analog circuits that power our embedded ReRAM and mixed-signal products.
Job Description:
In this role, you will take the lead on designing high-performance analog circuits, driving innovation in mixed-signal systems from concept through production. Youll partner closely with digital design, system architecture, and process engineering teams, playing a key role in bringing our next generation of memory products to market:
Design and develop complex analog circuits, including amplifiers, complex memory arrays, and LDOs, ensuring reliability and performance
Collaborate with cross-functional teams to define system specifications and architecture, translating requirements into actionable designs
Conduct thorough simulations and analyses to validate designs, using tools such as Cadence Virtuoso and Siemens Solido while identifying and mitigating risks early in the design process
Oversee the transition of designs from prototype to production, ensuring compliance with quality and industry standards
Apply deep expertise in analog circuit design - including amplifiers, voltage references, comparators, and ADCs/DACs - to push the boundaries of performance.

Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are looking for exceptional talent to join our team as a Hardware Engineer.
Your Day to Day:
Lead end-to-end hardware development, from architecture and design to testing and production
Design and develop complex electronic systems, including schematics, PCB layout guidance, and component selection
Drive system integration, bring-up, debugging, and validation processes
Collaborate with firmware, software, mechanical, and product teams to ensure seamless system performance
Identify technical risks and propose effective mitigation strategies
Support manufacturing, including design for manufacturability (DFM) and design for testability (DFT)
Analyze and improve system performance, reliability, and cost
Mentor junior engineers and contribute to team knowledge sharing

Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

We are seeking an experienced Technical Lead - Hardware Engineering to lead the technical development of advanced electronic systems and manage external hardware design contractors throughout the product lifecycle. The role is responsible for defining the hardware architecture, supervising outsourced development, ensuring engineering quality, and supporting projects from concept through production.
Key Responsibilities
Define hardware architecture and technical requirements. Lead and manage external hardware design contractors. Review and approve schematics, PCB layouts, and design documentation. Oversee High-Speed PCB design, SI/PI, DFM, and design reviews. Lead prototype bring-up, debugging, validation, and production support. Collaborate with system, FPGA, Firmware, Software, Mechanical, Manufacturing, and Quality teams. Drive technical problem solving and continuous improvement.

we are seeking a Physical Design Technical Leader.

Required Senior SOC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

We are developing leading edge products, manufactured on leading edge technologies.
We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Assume full ownership of mechanical and thermal design of Annapurna ICs.
Engage with product architect and design teams on future products package and assembly needs
Perform package level thermal simulations.
Perform package level mechanical simulations.
Lead and design thermal and mechanical measurements of ICs.
Explore and provide recommendations on both available and future packaging and assembly technologies for Annapurnas products.
Engage with substrate and assembly vendors on future technologies roadmap.
In collaboration with HW Dev team optimize mechanical vs. thermal tradeoffs.
Ensure testability of the ICs in collaboration with Test Engineer team.

Required Senior DDR Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

At our company, we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of our customers every single day.

The position is relevant to all our sites: Herzliya, Haifa and Jerusalem

In this role, you'll participate in the architecture of next-generation PHY, conduct RTL implementation of the micro-architecture, and participate in clearly defining specification, testing, and verification of the PHY design.
Work in collaboration with CAD, PD teams to implement RTL design into GDS, run various design verification flows and provide guidelines to other designers, and participate in establishing CAD and design methodologies for correct-by-construction designs

We are looking for a Product Design Team Lead to own design across our three product lines - Photo, Video, and Real Estate - and lead the team of designers who build them.

This is a player-coach role: roughly 40% hands-on design, 60% leadership. You will manage a team of designers, and hold the full design picture across the product. You own design decisions end-to-end .

This role offers the opportunity to directly shape Imagen's product experience at a category-defining moment, working closely with the heads of product, engineering, and leadership.

Responsibilities
Manage product designers Team including 1:1s, performance reviews, growth, and professional development.
Drive design excellence and elevate the team's craft through structured feedback, critique, and leadership.
Hold decision authority across Core, Video, and Real Estate.
Stay hands-on on core initiatives; lead by doing, not just reviewing.
Build and evolve the design system, patterns, and standards.
Drive design workflows through AI and industry best practices.

Required Design Verification - Intern
job requisition id
2604481
Your Team, Your Impact
Join a highly skilled development team, driving the development of our next-generation network switches. Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification.
As an intern, you will learn switch architecture, design and verification development tools and modern methodologies. You will be doing hands-on development tasks and learn to become an experienced engineer. You will learn system verilog, UVM, Python, C++, using AI tools, and how to implement and verify complex features. You will investigate and implement new protocols and features and verify them to tapeout quality. We are looking for excellent students, able to handle complex problems, with excellent people relations and collaboration skills.
What You Can Expect:
Implement new features in design and verification.
Reach high-frequency, high-performance, and low-power targets.
Write a verification test plan using random techniques and coverage analysis.
Develop a complex object-oriented random verification environment using System Verilog/UVM.
Create tests and tune the environment to achieve coverage goals.
Own and debug failures in simulation to root cause problems.
Analysis/closure of code and functional coverage.
Use scripting languages to automate repetitive tasks and improve efficiency.